DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Applicant's amendment to the claims, filed on July 15th, 2026, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
Applicant's response filed on July 15th, 2026 is acknowledged and isanswered as follows.
Applicant's remarks, see pgs. 10-11, with respect to the objection of claim 1 under formalities have been fully considered and are persuasive. Therefore, the objection of claim 1 has been withdrawn.
Applicant's arguments, see pgs. 11-14, with respect to the rejections of claims 1, 3-6, 15-16 and 2 under 35 U.S.C 102 (a)(1) and/or 35 U.S.C 103(a) have been considered but are not persuasive in view of the following reasons.
Applicant argues that Liebmann fails to disclose “wherein no transistor is formed in the second device layer overlapping the first transistor in the first device layer along a vertical direction” as recited in claims 1 and 16 (see Applicant’ argument and pgs. 11-13). The Examiner respectfully disagrees because claim 1 fails to further limit the reference orientation of the vertical direction and one of ordinary skill in the art can rotate Fig 1A of Liebmann to consider Y-direction as “a vertical direction”, and interprets that no transistor is formed in the second device layer (the layer comprising gate T4 and plurality of nanosheet channels 175) overlapping the first transistor (P1 transistor) in the first device layer along the Y-direction (see rotated Fig. 1A of Liebman below). Therefore, Liebmann discloses all limitations of amended claims 1 and 16.
In view of the foregoing reasons, the examiner believes that all Applicant's arguments and remarks are addressed. The examiner has determined that the previous Office Action is still proper based on the above responses. Therefore, the rejections are maintained.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-6 and 15-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by LIEBMANN et al. (Pub. No.: US 2022/0181322 A1), hereinafter as Liebmann.
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Regarding claim 1, Liebmann discloses a semiconductor structure in Figs. 1A-1B, comprising: a substrate (substrate 101), including a first device region (a region of P1 transistor) and a second device region (a region of N2 transistor) (see Fig. 1A and [0061]). a first device layer (the layer comprising gate T1 and plurality of nanosheet channels 173) on the substrate, wherein a first transistor (P1 transistor) at the first device region is in the first device layer (see Fig. 1A and [0062-0064]); a second device layer (the layer comprising gate T4 and plurality of nanosheet channels 175) on the first device layer (on insulating layer 171 that above P1 transistor), wherein a second transistor (N2 transistor) at the second device region is in the second device layer, and projections of the first transistor and the second transistor on a surface of the substrate are non-overlapped with each other (N2 transistor is not vertically overlapping with P2 transistor) (see Fig. 1A and [0065]); and an electrical interconnection structure (trace 153, track 114 and trace 123) in the first device layer and the second device layer, wherein the electrical interconnection structure is electrically connected to each of the first transistor and the second transistor (connecting gate T1 of P1 transistor to gate T4 of N2 transistor) (see Fig. 1A-1B and [0065-0067]), wherein no transistor is formed in the second device layer (no transistor in the layer comprising gate T4 and plurality of nanosheet channels 175) overlapping the first transistor (P1 transistor) in the first device layer along a vertical direction (Y-direction) (see rotated Fig. 1A of Liebman above).
Regarding claim 3, Liebmann discloses the semiconductor structure according to claim 1, wherein: the first transistor includes a first channel structure (channel of nanosheet channels 173) extending along a first direction (x-direction) and a first gate structure (gate T1) extending along a second direction (y-direction) (see Fig. 1A and [0063-0065]); the first gate structure is on a surface of the first channel structure (see Fig. 1A); and the second direction is perpendicular to the first direction (see Fig. 1A); and the second transistor includes a second channel structure (channel of nanosheet channels 175) extending along the first direction (x-direction) and a second gate structure (gate T4) extending along the second direction (y-direction) (see [0063-0065]); and the second gate structure is on a surface of the second channel structure (see Fig. 1A).
Regarding claim 4, Liebmann discloses the semiconductor structure according to claim 3, wherein: the first channel structure includes a plurality of first channel layers (plurality of nanosheet channels 173) overlapped with each other along a direction (Z direction) perpendicular to the surface of the substrate, and the first gate structure surrounds (gate T1) a surface of each first channel layer (see Fig. 1A and [0061], [0065]); and the second channel structure includes a plurality of second channel layers (plurality of nanosheet channels 1775) overlapped with each other along the direction perpendicular to the surface of the substrate, and the second gate structure (gate T4) surrounds a surface of each second channel layer (see Fig. 1A and [0061], [0065]); and/or the electrical interconnection structure includes a first plug on the first gate structure, a second plug on the second gate structure, and a first electrical connection structure electrically connected to each of the first plug and the second plug (not considering this limitation because of “and/or”); and the first gate structure and the second gate structure are electrically connected with each other through the first plug, the second plug and the first electrical connection structure (not considering this limitation because of “and/or”).
Regarding claim 5, Liebmann discloses the semiconductor structure according to claim 4, wherein: the first electrical connection structure (trace 123) is in the second device layer (see Fig. 1A and [0065]); the first plug (trace 153) is in the first device layer and the second device layer (see Fig. 1A and [0065]); and the second plug is in the second device layer (see Fig. 1A) (also because and/or limitation in claim 4, these limitation of claim 5 does not need to be considered).
Regarding claim 6, Liebmann discloses the semiconductor structure according to claim 3, wherein: the first transistor further includes a first source electrode (one first terminal structure) and a first drain electrode (second terminal structure) on two sides of the first gate structure (see Fig. 1A and [0069]); and the second transistor further includes a second source electrode (another one of first terminal structure) and a second drain electrode (third terminal structure) on two sides of the second gate structure (see Fig. 1A and [0069]).
Regarding claim 15, Liebmann discloses the semiconductor structure according to claim 1, further including a dielectric layer (insulating layer 171) between the first device layer and the second device layer (see Fig. 1A and [0062]).
Regarding claim 16, Liebmann discloses a forming method of a semiconductor structure in Figs. 1A-1B, comprising: forming a substrate (substrate 101), wherein the substrate including a first device region (a region of P1 transistor) and a second device region (a region of N2 transistor) (see Fig. 1A and [0061]); forming a first device layer (the layer comprising gate T1 and plurality of nanosheet channels 173) on the substrate, wherein a first transistor (P1 transistor) at the first device region is in the first device layer (see Fig. 1A and [0062-0064]); forming a second device layer (the layer comprising gate T4 and plurality of nanosheet channels 175) on the first device layer (on insulating layer 171 that above P1 transistor), wherein a second transistor (N2 transistor) at the second device region is in the second device layer, and projections of the first transistor and the second transistor on a surface of the substrate are non-overlapped with each other (N2 transistor is not vertically overlapping with P2 transistor) (see Fig. 1A and [0065]); and forming an electrical interconnection structure (trace 153, track 114 and trace 123), wherein the electrical interconnection structure is electrically connected to each of the first transistor and the second transistor (connecting gate T1 of P1 transistor to gate T4 of N2 transistor) (see Fig. 1A-1B and [0065-0067]); and forming a dielectric layer (insulating layer 171) between the first device layer and the second device layer (see Fig. 1A and [0062]), wherein no transistor is formed in the second device layer (no transistor in the layer comprising gate T4 and plurality of nanosheet channels 175) overlapping the first transistor (P1 transistor) in the first device layer along a vertical direction (Y-direction) (see rotated Fig. 1A of Liebman above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over LIEBMANN et al. (Pub. No.: US 2022/0181322 A1), hereinafter as Liebmann, as applied to claim 1 above.
Regarding claim 2, Liebmann discloses the semiconductor structure according to claim 1, wherein: a conductivity type of the first transistor (P type conductivity) is opposite to a conductivity type of the second transistor (N type conductivity) (see Fig. 1A and [0061]); the first transistor is an N-channel metal-oxide semiconductor (NMOS) transistor, and the second transistor is a P-channel metal-oxide semiconductor (PMOS) transistor (not considering this limitation) and/or a spacing range between the first transistor and the second transistor is from about 20 nanometers to about 100 nanometers (Liebmann fails to disclose this limitation).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have the semiconductor device comprising spacing range between the first transistor and the second transistor is from about 20 nanometers to about 100 nanometers because the semiconductor device are nano device and forming the spacing in nanometer range would maximize the number of devices in a wafer and circuit and would increase manufacturing profit. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over LIEBMANN et al. (Pub. No.: US 2022/0181322 A1), hereinafter as Liebmann, as applied to claim 1 above, and further in view of FULFORD et al. (Pub. No.: US 2023/0163185 A1), hereinafter as Fulford.
Regarding claim 2, Liebmann discloses the semiconductor structure according to claim 1, wherein: a conductivity type of the first transistor (P type conductivity) is opposite to a conductivity type of the second transistor (N type conductivity) (see Fig. 1A and [0061]); but fails to disclose the first transistor is an N-channel metal-oxide semiconductor (NMOS) transistor, and the second transistor is a P-channel metal-oxide semiconductor (PMOS) transistor; and/or a spacing range between the first transistor and the second transistor is from about 20 nanometers to about 100 nanometers (not considering this limitation).
Fulford discloses a semiconductor device comprising the first transistor is an N-channel metal-oxide semiconductor (NMOS) transistor (left lower stack 140 of transistor 110 being N type), and the second transistor is a P-channel metal-oxide semiconductor (PMOS) transistor (upper right stack 140 of transistor 120 being P type) (see Fig. 1B and [0051-0053], [0066]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the first transistor and the second transistor of Liebmann to be NMOS and PMOS as same as the semiconductor device of Fulford because the disclosure of Fulford NMOS and PMOS can be interchangeably formed by changing the conductivity type of the channel and source/drain for effectively forming integrated circuit.
Allowable Subject Matter
Claims 7-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claimed invention having: a first electrical contact structure electrically connected to the first source electrode; a second electrical contact structure electrically connected to the first drain electrode; a third electrical contact structure electrically connected to the second source electrode; and a fourth electrical contact structure electrically connected to the second drain electrode; and/or a third plug on the second electrical contact structure, a fourth plug on the third electrical contact structure, and a second electrical connection structure electrically connected to each of the third plug and the fourth plug, wherein the second electrical contact structure and the third electrical contact structure are electrically connected with each other through the third plug, the fourth plug and the second electrical connection structure as recited in claim 7. Claims 8-14 depend on claim 7, and therefore also include said claimed limitation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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