DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I invention, claims 1-10, 17-20, and newly added claims 21-26, in the reply filed on April 1, 2026, is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 9, 17, and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bu et al. (U.S. Pub. 2008/0308872) [Hereafter “Bu”].
Regarding claims 1-4 and 9, Bu [Fig.11] discloses an electronic circuit, comprising a plurality of transistors including:
at least one first MOS transistor of a first conductivity type arranged inside and on top of at least one first active area [200] of a semiconductor substrate [8];
at least one second MOS transistor of the second conductivity type arranged inside and on top of at least one second active area [100] of the semiconductor substrate;
each first active area [200] being delimited by a first insulating region [20] which is recessed with respect to a first surface of the semiconductor substrate by a first depth; and
each second active area [100] being delimited by a second insulating region [20] which is flush with the first surface of the semiconductor substrate [Fig.11], or which is recessed with respect to the first surface of the semiconductor substrate by a second depth smaller than the first depth;
wherein the first surface of the semiconductor substrate is topped with gate regions of the at least one first MOS transistor and of the at least one second MOS transistor, each gate region being insulated from the semiconductor substrate by a gate insulator layer [40A/40B];
wherein the at least one first and one second insulating regions [20] are shallow trench insulations [Para.54];
wherein the at least one first and one second insulating regions [region 20 between active areas 100 and 200] are adjacent to each other;
wherein the semiconductor substrate [8] includes silicon [Para.53] and the at least one first and one second insulating regions [20] include silicon oxide [Para.82].
Regarding claims 17 and 19-20, Bu [Fig.11] discloses an integrated circuit, comprising:
a semiconductor substrate [8] including a first active area [200] and a second active area [100];
a first transistor of a first conductivity type at the first active region [Para.54];
a second transistor of a second conductivity type at the second active area [Para.54]; and
a trench insulation [20] defining a boundary between the first active area and the second active area and including a top surface with a step such that a first portion of the top surface of the trench insulation next to the first active area [200] is lower than a second portion of the top surface of the trench insulation than to next to the second active area [100] [Fig.11];
wherein the top surface of the trench insulation [20] is below a top surface of the semiconductor substrate near the first active area [200], wherein the top surface of the trench insulation is substantially coplanar with the top surface of the semiconductor substrate near the second active area [100];
wherein the trench insulation [20] is silicon oxide [Para.82].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bu et al. (U.S. Pub. 2008/0308872).
Regarding claim 5, Bu discloses the insulating region [20] having a first depth and a second depth [region 20 between active areas 100 and 200], but fails to explicitly disclose wherein the first depth is greater than or equal to 120 Å, and the second depth is smaller than 120 Å. However, it would have been obvious to provide the depths as claimed, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim(s) 6-7 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bu et al. (U.S. Pub. 2008/0308872) in view of Okano (U.S. Pub. 2017/0062423).
Regarding claims 6-7, Bu fails to explicitly disclose the limitations of the claims. However, Okana [Fig.14] discloses an electronic circuit
wherein the gate region of at least one transistor among the plurality of transistors includes at least one counter-doping area [11; N-well] of a conductivity type opposite to the conductivity type of said at least one transistor [PT; PMOS], said at least one counter-doping area being positioned and sized to attenuate the hump effect of said at least one transistor, said at least one counter-doping area being positioned at the level of an overlapping area between the gate region [20] and the active area of said at least one transistor [Fig.14];
wherein the at least one transistor is the at least one first MOS transistor.
It would have been obvious to include the claimed limitations, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 10, Bu fails to explicitly disclose wherein the electronic circuit is contained in an electrically erasable and programmable non-volatile memory. However, Okano [Para.26] discloses wherein the electronic circuit is contained in an electrically erasable and programmable non-volatile memory. It would have been obvious to include wherein the electronic circuit is contained in an electrically erasable and programmable non-volatile memory, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Allowable Subject Matter
Claims 21-26 are allowed.
The following is an examiner’s statement of reasons for allowance: Prior art does not fairly disclose or make obvious the claimed device/method taken as a whole, and specifically, the limitations of
a first trench insulation in a semiconductor substrate delimiting a first active area of the semiconductor substrate;
a second trench insulation in the semiconductor substrate delimiting a second active area of the semiconductor substrate;
a first MOS transistor of a first conductivity type at the first active region; and
a second MOS transistor of a second conductivity type at the second active region;
wherein a top surface of the first trench insulation is recessed to a first depth below a top surface of the semiconductor substrate; and
wherein a top surface of the second trench insulation is recessed to a second depth below the top surface of the semiconductor substrate.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 8 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior art does not fairly disclose or make obvious the claimed device/method taken as a whole, and specifically, the limitations of
[Claim 8] wherein the first conductivity type is type N, each first MOS transistor being an NMOS transistor, and the second conductivity type is type P, each second MOS transistor being a PMOS transistor.
[Claim 18] wherein the first transistor is an NMOS transistor and the second transistor is a PMOS transistor.
Bu discloses the opposite transistor types being the first and the second transistors compared to the claimed requirements.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art is considered analogous art and discloses at least some of the claimed subject matter of the current invention. However, the prior art does not fairly disclose or make obvious the claimed device/method taken as a whole for the allowable claims as indicated above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BAC H AU whose telephone number is (571)272-8795. The examiner can normally be reached M-F 9:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BAC H AU/Primary Examiner, Art Unit 2898
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