Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This Office Action responds to the Application filed on 12/11/2023.
Claims 1-20 are pending.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Buechner et al. (U.S. Pub. No. 2012/0216160 A1) herein referenced as Buechner160 in view of Buechner et al (U.S. 2012/0266120 A1) herein referenced as Buechner120.
As per claim 1, Buechner160 discloses:
A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor (See Para [0067], i.e. program instructions may be provided to a processor) to:
determine a first glitch-inducing-window (GIW) for a first combinational logic (CL) gate of a circuit design (See Para [0008]-[0009], i.e. Glitches are caused by different arrival times of signals at the inputs of the gate, See Figure 2, i.e. calculating a glitch window as difference , See Para [0028], i.e. latest and earliest signal arrival times LAT, EAT at an output net N3, N5 of the gate X1, X3 under consideration are determined by static timing analysis and a glitch window is calculated as difference, See Para [0030]-[0041] & See Figures 3-8), subsequent to a modification of the circuit design that impacts the first CL gate (See Para [0028], i.e. at least one gate X3 which fan-out gate is directly connected to a fan-in gate of a resized gate, See Para [0051]-[0058], i.e. electrical circuit logic gates of the electrical circuit shown in FIG. 9 may be resized, See claim 1, i.e. resized gate for an incremental circuit calculation), based on arrival time ranges of first and second inputs of the first CL gate (See Para [0008]-[0009], i.e. Glitches are caused by different arrival times of signals at the inputs of the gate, See Figure 2, i.e. calculating a glitch window as difference , See Para [0028], i.e. latest and earliest signal arrival times LAT, EAT at an output net N3, N5 of the gate X1, X3 under consideration are determined by static timing analysis and a glitch window is calculated as difference, See Para [0030]-[0041] & See Figures 3-8).
Buechner160 does not teach: determine whether to retain the modification of the circuit design based on the first GIW.
However, Buechner120 teach: determine whether to retain the modification of the circuit design based on the first GIW (See Para [0028], i.e. S70 all configurations from the standard cell library for the gate X4 under consideration is tested by calculating respective upper bound for power consumption for each gate configuration. In step S80 gate configuration with minimum upper bound for power consumption is selected; and the gate-level design representation is modified according to the selected gate configuration in step S90, See claim 1, i.e. testing multiple configurations from the standard cell library for the selected gate by calculating respective upper bound for power consumption for each of the multiple configurations; selecting gate configuration of the multiple configurations with minimum upper bound for power consumption – See Para [0020]-[0028], – [prior art chose from different configurations, a selected configuration with minimum power consumption, would discard other configurations therefore determine whether to retain as cited above]).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of
Buechner120 into the teaching of Buechner160 because it would allow designer to
optimize an circuit that would reduce power consumption in the circuit (See Para
[0028]).
As per claim 2, Buechner160 and Buechner120 discloses all of the features of claim 1 as discloses above wherein Buechner160 also discloses wherein the stored instructions, when executed by the processor, further cause the processor to: determine a width of the first GIW based on the arrival time range of the first input; and determine a length of the first GIW based on the arrival time range of the second input (See Para [0028]-[0050] & Figures 3-8 –[From figure 8, prior art illustrate width and height of input including first and second (i.e. TGWN1…TGWN2) , considered as the determine as cited above]).
As per claim 3, Buechner160 and Buechner120 discloses all of the features of claim 2 as discloses above wherein Buechner160 also discloses wherein the stored instructions, when executed by the processor, further cause the processor to: determine whether to retain the modification based on a position of the first GIW relative to a glitch band of the first CL gate, wherein a width of the glitch band represents internal delays of the first CL gate (See Para [0034]-[0040], i.e. the glitch-window and d is the inertial delay of the gate X1).
As per claim 4, Buechner160 and Buechner120 discloses all of the features of claim 3 as discloses above wherein Buechner160 also discloses wherein the stored instructions, when executed by the processor, further cause the processor to: determine a glitch factor based on an area of the first GIW that lies within the glitch band and determine whether to retain the modification of the circuit design based on the glitch factor (See Para [0008]-[0009], i.e. Glitches are caused by different arrival times of signals at the inputs of the gate, See Figure 2, i.e. calculating a glitch window as difference , See Para [0028], i.e. latest and earliest signal arrival times LAT, EAT at an output net N3, N5 of the gate X1, X3 under consideration are determined by static timing analysis and a glitch window is calculated as difference, See Para [0030]-[0041] & See Figures 3-8).
As per claim 5, Buechner160 and Buechner120 discloses all of the features of claim 4 as discloses above wherein Buechner160 also discloses wherein the stored instructions, when executed by the processor, further cause the processor to: determine the glitch factor based on the area of the first GIW that lies within the glitch band and a total area of the first GIW (See Para [0008]-[0009], i.e. Glitches are caused by different arrival times of signals at the inputs of the gate, See Figure 2, i.e. calculating a glitch window as difference , See Para [0028], i.e. latest and earliest signal arrival times LAT, EAT at an output net N3, N5 of the gate X1, X3 under consideration are determined by static timing analysis and a glitch window is calculated as difference, See Para [0030]-[0041] & See Figures 3-8).
As per claim 6, Buechner160 and Buechner120 discloses all of the features of claim 1 as discloses above wherein Buechner160 also discloses wherein the stored instructions, when executed by the processor, further cause the processor to: determine a second GIW for the CL gate prior to the modification of the circuit design (See Para [0028]-[0050] & Figures 3-8, i.e. TGWN1…TGWN3). Wherein Buechner120 teach determine whether to retain the modification based on the first and second GIWs (See Para [0028], i.e. S70 all configurations from the standard cell library for the gate X4 under consideration – See Para [0020]-[0028]).
As per claim 7, Buechner160 and Buechner120 discloses all of the features of claim 1 as discloses above wherein Buechner160 also discloses wherein the stored instructions, when executed by the processor, further cause the processor to: compute a second GIW for a second CL gate impacted by the modification of the circuit design, wherein the second CL gate is within a fanout cone of the first CL gate (See Para [0011], i.e. fan-out gate is directly connected to a fan-in gate of a resized gate for an incremental circuit calculation, See Para [0026]-[0041]). Wherein Buechner120 teach determine whether to retain the modification of the circuit design based further on the second GIW of the second CL gate (See Para [0028], i.e. S70 all configurations from the standard cell library for the gate X4 under consideration – See Para [0020]-[0028]).
As per claim 8, Buechner160 and Buechner120 discloses all of the features of claim 1 as discloses above wherein Buechner160 also discloses wherein the stored instructions, when executed by the processor, further cause the processor to: determine a parameter and a glitch metric of the circuit design prior to the modification to the circuit design, wherein the parameter comprises one or more of a timing parameter, a power consumption parameter, and an area parameter (See Para [0028], i.e. power consumption), and wherein the glitch metric comprises one or more of glitch toggles associated with the first CL gate and glitch power associated with the glitch toggles (See Abstract, i.e. transition metric…signal transitions, See Para [0007]-[0009], See Para [0028]-[0041], i.e. transition metric for the output net); update the parameter and the glitch metric subsequent to the modification to the circuit design (See Para [0007]-[0009], See Para [0028]-[0041]). Wherein Buechner120 teach determine whether to retain the modification to the circuit design based further on the updated parameter and the updated glitch metric (See Para [0028], i.e. S70 all configurations from the standard cell library for the gate X4 under consideration – See Para [0020]-[0028]).
As per claim 9, Buechner160 discloses:
A method, comprising:
determining a first glitch factor for a first combinational logic (CL) gate of a circuit design (See Para [0008]-[0009], i.e. Glitches are caused by different arrival times of signals at the inputs of the gate, See Figure 2, i.e. calculating a glitch window as difference , See Para [0028], i.e. latest and earliest signal arrival times LAT, EAT at an output net N3, N5 of the gate X1, X3 under consideration are determined by static timing analysis and a glitch window is calculated as difference, See Para [0030]-[0041] & See Figures 3-8), based on arrival time ranges at first and second inputs of the first CL gate (See Para [0008]-[0009], i.e. Glitches are caused by different arrival times of signals at the inputs of the gate, See Figure 2, i.e. calculating a glitch window as difference , See Para [0028], i.e. latest and earliest signal arrival times LAT, EAT at an output net N3, N5 of the gate X1, X3 under consideration are determined by static timing analysis and a glitch window is calculated as difference, See Para [0030]-[0041] & See Figures 3-8) and an internal delay of the first CL gate (See Para [0030]-[0041, i.e. an inertial delay);
performing a first incremental modification to the circuit design, wherein the first incremental modification impacts the first CL gate (See Para [0028], i.e. at least one gate X3 which fan-out gate is directly connected to a fan-in gate of a resized gate, See Para [0051]-[0058], i.e. electrical circuit logic gates of the electrical circuit shown in FIG. 9 may be resized, See claim 1, i.e. resized gate for an incremental circuit calculation);
updating the first glitch factor for the first CL gate subsequent to the first incremental modification (See Para [0008]-[0009], i.e. Glitches are caused by different arrival times of signals at the inputs of the gate, See Figure 2, i.e. calculating a glitch window as difference , See Para [0028], i.e. latest and earliest signal arrival times LAT, EAT at an output net N3, N5 of the gate X1, X3 under consideration are determined by static timing analysis and a glitch window is calculated as difference, See Para [0030]-[0041] & See Figures 3-8, See Para [0042]-[0059]).
Buechner160 does not teach: determining whether to retain the first incremental modification of the circuit design based on the updated first glitch factor for the first CL gate and an optimization criterion.
However, Buechner120 teach: determining whether to retain the first incremental modification of the circuit design based on the updated first glitch factor for the first CL gate and an optimization criterion (See Para [0028], i.e. S70 all configurations from the standard cell library for the gate X4 under consideration is tested by calculating respective upper bound for power consumption for each gate configuration. In step S80 gate configuration with minimum upper bound for power consumption is selected; and the gate-level design representation is modified according to the selected gate configuration in step S90, See claim 1, i.e. testing multiple configurations from the standard cell library for the selected gate by calculating respective upper bound for power consumption for each of the multiple configurations; selecting gate configuration of the multiple configurations with minimum upper bound for power consumption – See Para [0020]-[0028], – [prior art chose from different configurations, a selected configuration with minimum power consumption, would discard other configurations therefore determine whether to retain as cited above]).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of
Buechner120 into the teaching of Buechner160 because it would allow designer to
optimize an circuit that would reduce power consumption in the circuit (See Para
[0028]).
As per claim 10, Buechner160 and Buechner120 discloses all of the features of claim 9 as discloses above wherein Buechner160 also discloses wherein determining the first glitch factor comprises: determining a first glitch inducing window (GIW) for the first CL gate based on the arrival time ranges at the first and second inputs to the first CL gate; determining a glitch band of the first CL gate based on the internal delay of the first CL gate; and determining the first glitch factor based on an area of the first GIW that lies within the glitch ban (See Para [0008]-[0009], i.e. Glitches are caused by different arrival times of signals at the inputs of the gate, See Figure 2, i.e. calculating a glitch window as difference , See Para [0028], i.e. latest and earliest signal arrival times LAT, EAT at an output net N3, N5 of the gate X1, X3 under consideration are determined by static timing analysis and a glitch window is calculated as difference, See Para [0030]-[0041] & See Figures 3-8).
As per claim 11, Buechner160 and Buechner120 discloses all of the features of claim 10 as discloses above wherein Buechner160 also discloses wherein determining the first GIW comprises: determining a width of the first GIW based on the arrival time range at the first input to the first CL gate; and determining a length of the first GIW based on the arrival time range at the second input to the first CL gate (See Para [0028]-[0050] & Figures 3-8 –[From figure 8, prior art illustrate width and height of input including first and second (i.e. TGWN1…TGWN2) , considered as the determine as cited above]).
As per claim 12, Buechner160 and Buechner120 discloses all of the features of claim 9 as discloses above wherein Buechner160 also discloses wherein performing the first incremental modification comprises replacing the first CL gate with a replacement CL gate, and wherein updating the first glitch factor comprises: determining a second GIW of the replacement CL gate based on arrival time ranges at first and second inputs to the replacement CL gate; determining a glitch band of the replacement CL gate based on the internal delay of the replacement CL gate; and updating the first glitch factor based on an area of the second GIW of the replacement CL that lies within the glitch band of the replacement CL (See Para [0028], i.e. S70 all configurations from the standard cell library for the gate X4 under consideration is tested by calculating respective upper bound for power consumption for each gate configuration. In step S80 gate configuration with minimum upper bound for power consumption is selected; and the gate-level design representation is modified according to the selected gate configuration in step S90, See claim 1, i.e. testing multiple configurations from the standard cell library for the selected gate by calculating respective upper bound for power consumption for each of the multiple configurations; selecting gate configuration of the multiple configurations with minimum upper bound for power consumption – See Para [0020]-[0060], See Figures 7-10).
As per claim 13, Buechner160 and Buechner120 discloses all of the features of claim 9 as discloses above wherein Buechner160 also discloses determining a parameter and a glitch metric of the circuit design prior to the performing the first incremental modification, wherein the parameter comprises one or more of a timing parameter, a power consumption parameter, and an area parameter (See Para [0028], i.e. power consumption), and wherein the glitch metric comprises one or more of glitch toggles associated with the first CL gate and glitch power associated with the glitch toggles (See Abstract, i.e. transition metric…signal transitions, See Para [0007]-[0009], See Para [0028]-[0041], i.e. transition metric for the output net); updating the parameter and the glitch metric subsequent to performing the first incremental modification (See Para [0007]-[0009], See Para [0028]-[0041]). Wherein, Buechner120 teach determining whether to retain the first incremental modification based further on the updated parameter and the updated glitch metric (See Para [0028], i.e. S70 all configurations from the standard cell library for the gate X4 under consideration – See Para [0020]-[0028]).
As per claim 14, Buechner160 and Buechner120 discloses all of the features of claim 13 as discloses above wherein Buechner160 also discloses wherein determining the parameter and the glitch metric of the circuit design prior to performing the first incremental modification comprises one or more of: simulating operation of the circuit design; emulating the operation of the circuit design; and prototyping the operation of the circuit design (See Para [0003]-[0010], i.e. simulation).
As per claim 15, Buechner160 and Buechner120 discloses all of the features of claim 13 as discloses above wherein Buechner160 also discloses performing a second incremental modification to the circuit design, wherein the second incremental modification impacts the first CL gate; updating the parameter and the glitch metric subsequent to the second incremental modification (See Para [0028], i.e. at least one gate X3 which fan-out gate is directly connected to a fan-in gate of a resized gate, See Para [0051]-[0058], i.e. electrical circuit logic gates of the electrical circuit shown in FIG. 9 may be resized, See claim 1, i.e. resized gate for an incremental circuit calculation). Wherein, Buechner120 teach determining whether to retain the second incremental modification based on the corresponding updated parameter, updated glitch metric, and updated glitch factor, and the optimization criterion (See Para [0028], i.e. S70 all configurations from the standard cell library for the gate X4 under consideration – See Para [0020]-[0028]).
As per claim 16, Buechner160 and Buechner120 discloses all of the features of claim 9 as discloses above wherein Buechner160 also discloses determining a second glitch factor for a second CL gate within a fanout cone of the first CL gate, prior to the first incremental modification, based on arrival time ranges of first and second inputs of the second CL gate and an internal delay of the second CL gate; updating the second glitch factor for the second CL gate subsequent to the first incremental modification (See Para [0028], i.e. at least one gate X3 which fan-out gate is directly connected to a fan-in gate of a resized gate, See Para [0051]-[0058], i.e. electrical circuit logic gates of the electrical circuit shown in FIG. 9 may be resized, See claim 1, i.e. resized gate for an incremental circuit calculation). Wherein, Buechner120 determining whether to retain the first incremental modification to the circuit design based further on the updated second glitch factor for the second CL gate (See Para [0028], i.e. S70 all configurations from the standard cell library for the gate X4 under consideration – See Para [0020]-[0028]).
As per claim 17, Buechner160 discloses:
A system comprising: a memory storing instructions; and a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor (See Para [0067], i.e. program instructions may be provided to a processor) to,
determine a glitch factor for a combinational logic (CL) gate of a circuit based (See Para [0008]-[0009], i.e. Glitches are caused by different arrival times of signals at the inputs of the gate, See Figure 2, i.e. calculating a glitch window as difference , See Para [0028], i.e. latest and earliest signal arrival times LAT, EAT at an output net N3, N5 of the gate X1, X3 under consideration are determined by static timing analysis and a glitch window is calculated as difference, See Para [0030]-[0041] & See Figures 3-8), on arrival time ranges at first and second inputs of the CL gate (See Para [0008]-[0009], i.e. Glitches are caused by different arrival times of signals at the inputs of the gate, See Figure 2, i.e. calculating a glitch window as difference , See Para [0028], i.e. latest and earliest signal arrival times LAT, EAT at an output net N3, N5 of the gate X1, X3 under consideration are determined by static timing analysis and a glitch window is calculated as difference, See Para [0030]-[0041] & See Figures 3-8) and an internal delay of the CL gate (See Para [0030]-[0041, i.e. an inertial delay);
update the glitch factor for the CL gate subsequent to a modification to the circuit design that impacts the CL gate (See Para [0028], i.e. at least one gate X3 which fan-out gate is directly connected to a fan-in gate of a resized gate, See Para [0030]-[0041] & See Figures 3-8, See Para [0051]-[0058], i.e. electrical circuit logic gates of the electrical circuit shown in FIG. 9 may be resized, See claim 1, i.e. resized gate for an incremental circuit calculation).
Buechner160 does not teach: determine whether to retain the incremental modification to the circuit design based on the updated glitch factor for the CL gate and an optimization criterion.
However, Buechner120 teach: determine whether to retain the incremental modification to the circuit design based on the updated glitch factor for the CL gate and an optimization criterion (See Para [0028], i.e. S70 all configurations from the standard cell library for the gate X4 under consideration is tested by calculating respective upper bound for power consumption for each gate configuration. In step S80 gate configuration with minimum upper bound for power consumption is selected; and the gate-level design representation is modified according to the selected gate configuration in step S90, See claim 1, i.e. testing multiple configurations from the standard cell library for the selected gate by calculating respective upper bound for power consumption for each of the multiple configurations; selecting gate configuration of the multiple configurations with minimum upper bound for power consumption – See Para [0020]-[0028], – [prior art chose from different configurations, a selected configuration with minimum power consumption, would discard other configurations therefore determine whether to retain as cited above]).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of
Buechner120 into the teaching of Buechner160 because it would allow designer to
optimize an circuit that would reduce power consumption in the circuit (See Para
[0028]).
As per claim 18, Buechner160 and Buechner120 discloses all of the features of claim 17 as discloses above wherein Buechner160 also discloses wherein the instructions when executed, further cause the processor to: determine a glitch inducing window (GIW) for the CL gate based on the arrival time ranges at the first and second inputs to the CL gate; determine a glitch band of the CL gate based on the internal delay of the CL gate; and determine the glitch factor based on an area of the GIW that lies within the glitch band (See Para [0008]-[0009], i.e. Glitches are caused by different arrival times of signals at the inputs of the gate, See Figure 2, i.e. calculating a glitch window as difference , See Para [0028], i.e. latest and earliest signal arrival times LAT, EAT at an output net N3, N5 of the gate X1, X3 under consideration are determined by static timing analysis and a glitch window is calculated as difference, See Para [0030]-[0041] & See Figures 3-8).
As per claim 19, Buechner160 and Buechner120 discloses all of the features of claim 18 as discloses above wherein Buechner160 also discloses wherein the instructions when executed, further cause the processor to: determine a width of the GIW based on the arrival time range at the first input to the CL gate; and determine a length of the GIW based on the arrival time range at the second input to the CL gate (See Para [0028]-[0050] & Figures 3-8 –[From figure 8, prior art illustrate width and height of input including first and second (i.e. TGWN1…TGWN2) , considered as the determine as cited above]).
As per claim 20, Buechner160 and Buechner120 discloses all of the features of claim 9 as discloses above wherein Buechner160 also discloses wherein the modification to the circuit design replaces the CL gate with a replacement CL gate, and wherein the instructions when executed, further cause the processor to update the glitch factor by: determining a GIW of the replacement CL gate based on arrival time ranges at first and second inputs to the replacement CL gate; determining a glitch band of the replacement CL gate based on the internal delay of the replacement CL gate; and updating the glitch factor based on an area of the GIW of the replacement CL that lies within the glitch band of the replacement CL (See Para [0028], i.e. at least one gate X3 which fan-out gate is directly connected to a fan-in gate of a resized gate, See Para [0030]-[0041] & See Figures 3-8, See Para [0051]-[0058], i.e. electrical circuit logic gates of the electrical circuit shown in FIG. 9 may be resized, See claim 1, i.e. resized gate for an incremental circuit calculation).
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHA T NGUYEN whose telephone number is (571)270-1405. The examiner can normally be reached M-F 8:00AM-5:00PM.
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/NHA T NGUYEN/Primary Examiner, Art Unit 2851
