Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in CN on 08 Nov 2023. It is noted, however, that applicant has not filed a certified copy of the PCT/CN2023/130528 application as required by 37 CFR 1.55. NOTE: PCT/CN2023/130528 is not a foreign application.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that use the word “circuitry” but are nonetheless not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because the claim limitation recite sufficient structure, materials, or acts to entirely perform the recited function. Such claim limitation(s) is/are: “circuitry” in claims 1-7. See MPEP 2181.
Because this/these claim limitation(s) is/are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 2 recites the limitations, however it is missing the limitations after “wherein the----”???. Amendments/clarifications are required.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 14 recites “wherein the interior pixel is located in a three-dimensional image”. Claim 14 depends from claim 8. Claim 8 recites “ – an interior pixel of the object, wherein the object is represented by pixels of an image”. The recital in claim 14 renders the claim indefinite because how the interior pixel can be located in an image as recited in claim 8 and also in a three dimensional image as recited in claim 14?. Amendments/clarification are required.
Claim 17 recites the limitation "the minimum distance" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 19 recites the limitation "the minimum distance" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-5, 7-9, 11-12, 15-16 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kita, Koji (EP1562145A1) hereafter Kita.
1. Regarding claim 1, Kita discloses one or more processors (figs 1-5 shows an apparatus with one or more processors (i.e CPU 17), see paras 0009-0012,0025-0031 and 0045-0048 shows and discloses one or more processors comprising hardware (i.e circuitry to) comprising:
circuitry to:
identify a first edge pixel of an object (figs 1-2, element 2 is an object) that shares a same first index with an interior pixel of the object, wherein the object is represented by pixels of an image (figs 1-2, 5 shows an image of the object (i.e film) represented by the pixels as seen in fig 5 and
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Pixel P2 is a first edge pixel (detected/identified pixel is the boundary (edge) pixel along the line L1, para 0048) that shares a same first index with an interior pixel O meeting the above claim limitations, examiner notes that the specifics of a first edge pixel, an interior pixel and “identify” are not required by the current claim);
select a subset of pixels of the image according to a constraint that limits the subset according to a location of the identified first edge pixel within the image (fig 5, paras 0031, 0037-0044 shows the pixels (i.e the subset of the pixels in the image, also para 0043 discloses detecting two or more normal pixels P on each side across target pixel O) according to a constraint that limits (i.e the angular interval between adjacent search lines L) the subset according to a location of the identified first edge pixel P2 within the image meeting the above claim limitations, examiner notes that the specifics of “subset of the pixels”, selecting and constraints are not required by the current claim); and
identify a second edge pixel of the object based, at least in part, on distances between the interior pixel and edge pixels within the selected subset of pixels (fig 5 and paras 0039, 0048 shows and discloses identify a second edge pixel P1 of the object 2 based, at least in part, on distances between the interior pixel O and edge pixels within the selected subset of pixels (I.e boundary or edge pixels P as seen in fig 5) meeting the above claim limitations, examiner notes that the specifics of a second edge pixel and identify are not required by the current claim).
2. Regarding claim 2 as best understood by the examiner, Kita discloses the one or more processors of claim 1, wherein the circuitry is to calculate a minimum distance between the second edge pixel and the interior pixel based, at least in part, on calculations distances from the interior pixel to only the edge pixels within the selected subset of pixels, wherein the (Fig 5, para 0039 discloses the short “i.e minimum” distances between the target pixel O (i.e interior pixel) and the normal pixels P (second edge pixel P1) meeting the above claim limitations).
3. Regarding claim 4, Kita discloses the one or more processors of claim 1, wherein the circuitry is to identify the first edge pixel, the second edge pixel, and the edge pixels within the selected subset of pixels, in parallel (fig 5 shows wherein the circuitry is to identify the first edge pixel P2, the second edge pixel P1, and the edge pixels P within the selected subset of pixels, in parallel (i.e the top edge pixels are parallel with the bottom edge pixels and the left edge pixels are parallel with the right edge pixels meeting the claim limitations).
4. Regarding claim 5, Kita discloses the one or more processors of claim 1, are to generate a data structure identifying the first edge pixel, second edge pixel, and edge pixels within the selected subset of pixels of the object (fig 5 shows the data structure (i.e pixel map) identifying the first edge pixel, second edge pixel, and edge pixels within the selected subset of pixels of the object, examiner notes that the specifics of “a data structure’ are not required by the current claim).
5. Regarding claim 7, Kita discloses the one or more processors of claim 1, wherein the image in which the interior pixel is located is a two-dimensional image (fig 5 shows the image in which the interior pixel is located is a two-dimensional image).
6. Claim 8 is a corresponding method claim of claim 1. See the corresponding explanation of claim 1.
7. Claim 9 is a corresponding method claim of claim 2. See the corresponding explanation of claim 2.
8. Claim 11 is a corresponding method claim of claim 4. See the corresponding explanation of claim 4. Fig 4 shows the algorithm/plurality of software threads/instructions meeting the claim limitations.
9. Claim 12 is a corresponding method claim of claims 4 and 5. See the corresponding explanation of claims 4 and 5. Fig 4 shows the algorithm/plurality of software threads/instructions meeting the claim limitations.
10. Regarding claim 15, Kita discloses a system, (figs 1-5 shows an apparatus/system with one or more processors (i.e CPU 17), see paras 0009-0012,0025-0031 and 0045-0048 shows and discloses one or more processors comprising hardware (i.e circuitry to) comprising: one or more processors (figs 1-5 shows an apparatus/system with one or more processors (i.e CPU 17), see paras 0009-0012,0025-0031 and 0045-0048 shows and discloses one or more processors comprising hardware (i.e circuitry to) to: identify a first edge pixel of an object (figs 1-2, element 2 is an object) that shares a same first index with an interior pixel of the object, wherein the object is represented by pixels of an image (figs 1-2, 5 shows an image of the object (i.e film) represented by the pixels as seen in fig 5 and
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Pixel P2 is a first edge pixel (detected/identified pixel is the boundary (edge) pixel along the line L1, para 0048) that shares a same first index with an interior pixel O meeting the above claim limitations, examiner notes that the specifics of a first edge pixel, an interior pixel and “identify” are not required by the current claim);
select a subset of pixels of the image according to a constraint that limits the subset according to a location of the identified first edge pixel within the image (fig 5, paras 0031, 0037-0044 shows the pixels (i.e the subset of the pixels in the image, also para 0043 discloses detecting two or more normal pixels P on each side across target pixel O) according to a constraint that limits (i.e the angular interval between adjacent search lines L) the subset according to a location of the identified first edge pixel P2 within the image meeting the above claim limitations, examiner notes that the specifics of “subset of the pixels” and constraints are not required by the current claim); and
identify a second edge pixel of the object based, at least in part, on distances between the interior pixel and edge pixels within the selected subset of pixels (fig 5 and paras 0039, 0048 shows and discloses identify a second edge pixel P1 of the object 2 based, at least in part, on distances between the interior pixel O and edge pixels within the selected subset of pixels (I.e boundary or edge pixels P as seen in fig 5) meeting the above claim limitations, examiner notes that the specifics of a second edge pixel and identify are not required by the current claim).
11. Claim 16 is s corresponding system claim of claim 2. See the corresponding explanation of claim 2.
12. Claim 19 is a corresponding system claim of claims 2 and 4. See the corresponding explanation of claims 2 and 4.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 6, 10, 13 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kita in view of Milne et al. (US9251607) hereafter Milne.
13. Regarding claim 3, Kita discloses the one or more processors of claim 1, wherein the circuitry is to (Fig 5, para 0039 discloses the short “i.e minimum” distances between the target pixel O (i.e interior pixel) and the normal pixels P (second edge pixel P2) meeting the above claim limitations of generate a distance transform). Kita is silent and however fails to disclose generate a distance transform. Milne discloses generating a distance transform (figs 2, 5, col 11 lines 5 through 61 shows and disclose distance transform to be generated as seen in table 1, examiner notes that the specifics of distance transform are not required by the current claim). Before the effective filing date of the invention was made, Milne and Kita are combinable because they are from the same filed of endeavor and are analogous art of image processing. The suggestion/motivation would be an efficient, faster and reduced bandwidth system/device at col 3 lines 58-67. Therefore, it would be obvious and within one of ordinary skill in the art to have recognized the advantages of Milne in the apparatus of Kita to obtain the invention as specified in claim 3.
14. Regarding claim 6, Kita discloses the one or more processors of claim 1, wherein the circuitry is (Fig 5 and its disclosure). Kita is silent and however fails to disclose to perform a binary search.
Milne discloses perform a binary search (figs 2, 5 and col 11 lines 48-62 discloses assigning the membership values of 1 and 0 (i.e the binary search) to identify the two edge pixels (i.e the zero edge and the central region edge) of the object within the same row of pixels (i.e subset of the pixels) meeting the above claim limitations, examiner notes that the specifics of a binary search are not required by the current claim). Before the effective filing date of the invention was made, Milne and Kita are combinable because they are from the same filed of endeavor and are analogous art of image processing. The suggestion/motivation would be an efficient, faster and reduced bandwidth system/device at col 3 lines 58-67. Therefore, it would be obvious and within one of ordinary skill in the art to have recognized the advantages of Milne in the apparatus of Kita to obtain the invention as specified in claim 6.
15. Claim 10 is a corresponding method claim of claim 3. See the explanation of claim 3. Examiner notes that due to the recital of one or more, only one distance transform is required by the claim.
16. Regarding claim 13, Kita discloses the method of claim 8, wherein a minimum distance between the second edge pixel and the interior pixel is calculated (Fig 5, para 0039 discloses the short “i.e minimum” distances between the target pixel O (i.e interior pixel) and the normal pixels P (second edge pixel P2) meeting the above claim limitations of generate a distance transform), in parallel (i.e the top edge pixels are parallel with the bottom edge pixels and the left edge pixels are parallel with the right edge pixels meeting the claim limitations),
Milne discloses using one or more threads of a graphics processing unit (GPU) (col 5 lines 26-45, col 11 lines 24-27 discloses wherein the one or more processors comprise a central processing unit (CPU) that is to cause a graphics processing unit (GPU) to calculate the minimum distance). Before the effective filing date of the invention was made, Milne and Kita are combinable because they are from the same filed of endeavor and are analogous art of image processing. The suggestion/motivation would be an efficient, faster and reduced bandwidth system/device at col 3 lines 58-67. Therefore, it would be obvious and within one of ordinary skill in the art to have recognized the advantages of Milne in the apparatus of Kita to obtain the invention as specified in claim 13.
17. Regarding claim 18, Kita discloses the system of claim 15, wherein the one or more processors comprise a central processing unit (CPU) (fig 5 shows wherein the circuitry is to identify the first edge pixel P2, the second edge pixel P1, and the edge pixels P within the selected subset of pixels, in parallel (i.e the top edge pixels are parallel with the bottom edge pixels and the left edge pixels are parallel with the right edge pixels meeting the claim limitations).
Milne discloses to cause a GPU to calculate the minimum distance (col 5 lines 26-45, col 11 lines 24-27 discloses wherein the one or more processors comprise a central processing unit (CPU) that is to cause a graphics processing unit (GPU) to calculate the minimum distance). Before the effective filing date of the invention was made, Milne and Kita are combinable because they are from the same filed of endeavor and are analogous art of image processing. The suggestion/motivation would be an efficient, faster and reduced bandwidth system/device at col 3 lines 58-67. Therefore, it would be obvious and within one of ordinary skill in the art to have recognized the advantages of Milne in the apparatus of Kita to obtain the invention as specified in claim 18.
Claim 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kita in view of Pfister et al. (US20080260238) hereafter Pfister.
18. Regarding claim 14, Kita discloses the method of claim 8, wherein the interior pixel is located in a 2D image as seen in fig 5. Kita is silent and however fails to disclose a three-dimensional image.
Pfister discloses a three-dimensional image in fig 2 para 0042. Before the effective filing date of the invention was made, Kita and Pfister are combinable because they are from the same filed of endeavor and are analogous art of image processing. The suggestion/motivation would be a reduced error processing method/system in para 0012. Therefore, it would be obvious and within one of ordinary skill in the art to have recognized the advantages of Pfister in the method of Kita to obtain the invention as specified in claim 14.
19. Regarding claim 20, Kita discloses the system of claim 15, wherein the one or more processors are to (fig 5 shows the data structure (i.e pixel map) identifying the first edge pixel, second edge pixel, and edge pixels within the selected subset of pixels of the object, examiner notes that the specifics of “a data structure’ are not required by the current claim)
Pfister discloses and shows the object image stored in a shared graphics processing unit (GPU) memory 106 and in para 0062. Before the effective filing date of the invention was made, Kita and Pfister are combinable because they are from the same filed of endeavor and are analogous art of image processing. The suggestion/motivation would be a reduced error processing method/system in para 0012. Therefore, it would be obvious and within one of ordinary skill in the art to have recognized the advantages of Pfister in the system of Kita to obtain the invention as specified in claim 20.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kita in view of
KUBOTA et al., (US20200184593) hereafter KUBOTA.
20. Regarding claim 17, Kita discloses the system of claim 15, wherein the one or more processors are to identify the minimum distance between the interior pixel and the second edge pixel (fig 5 and its disclosure shows and discloses wherein the one or more processors are to identify the minimum distance between the interior pixel and the second edge pixel)
KUBOTA discloses by causing one thread of a graphics processing unit (GPU) to be performed per row of the first index in parallel with one or more other threads of the GPU (figs 1-5, and paras 0007, 0034, 0043, 0071-0074 shows and discloses performing the processing one thread per row of an image in which the first index pixel is located to identify edge pixels (boundary pixels) of each row of the image in parallel meeting the claim limitations). Before the effective filing date of the invention was made, Kita and KUBOTA are combinable because they are from the same filed of endeavor and are analogous art of image processing. The suggestion/motivation would be an advantageous processing system at para 0007-0008. Therefore, it would be obvious and within one of ordinary skill in the art to have recognized the advantages of KUBOTA in the system of Kita to obtain the invention as specified in claim 17.
Examiner's Note: Examiner has cited figures, and paragraphs in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested for the applicant, in preparing the responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. Examiner has also cited references in PTO892 but not relied on, which are relevant and pertinent to the applicant’s disclosure, and may also be reading (anticipatory/obvious) on the claims and claimed limitations. Applicant is advised to consider the references in preparing the response/amendments in-order to expedite the prosecution.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAYESH PATEL whose telephone number is (571)270-1227. The examiner can normally be reached IFW Mon-FRI.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Bee can be reached at 571-270-5183. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAYESH PATEL/
Primary Examiner
Art Unit 2677
/JAYESH A PATEL/Primary Examiner, Art Unit 2677
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