Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 2 has been objected for claim language “prior to production of the trench, an antireflection layer is applied to a part of the top of the semiconductor wafer that is not covered by the front terminal contacts, and wherein, after the removal of the insulating layer on a part of a top of the front terminal contact, the antireflection layer is removed from the part of the top of the front terminal contact”. Claim langue “the antireflection layer is removed from the part of the top of the front terminal contact” is conflicting with the first part which states that the antireflection layer is not applied on the front terminal contacts.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the 20claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-7 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lucow et al. (US 2017/0213922, hereinafter Lucow) in view of Fidaner et al. (US 2014/0196779, hereinafter Fidaner).
With respect to claim 1, Lucow discloses a method of producing a stacked multi-junction solar cell with a front side contacted through the rear side (Fig. 27), the method comprising: providing a semiconductor wafer (Para 0113 – wafer) having a top (top side of the wafer), a bottom (rear side of the wafer), and at least two solar cell stacks (Fig. 27 – there are two stacks), each of the at least two solar cell stacks has a Ge substrate that forms the bottom of the semiconductor wafer (Para 0078- substate comprises of germanium), a Ge subcell (Para 0003), and at least two III-V subcells (Para 0033 & 0113 – heteroepitaxial layer 2704 - the heteroepitaxial layer comprises a first subcell and at least one additional subcell overlying the first subcell; and at least one of the first subcell or the at least one additional subcell comprises an alloy comprising one or more elements from group III of the periodic table, N, As, and an element selected from Sb, Bi and a combination thereof); applying a front terminal contact (2702A) to the top of the semiconductor wafer for each of the two solar cell stacks (right and left side 2702A’s); forming a trench (opening inside 2705) that has a continuous lateral wall and extends into the semiconductor wafer from the top of the semiconductor wafer (Fig. 27); producing a hole extending from a bottom of the trench to the bottom of the semiconductor wafer (Fig. 27) and having a continuous lateral wall and a perimeter in cross section for each of the two solar cell stacks (Fig. 27 – opening in the wafer has continuous later walls); applying a dielectric insulating layer (2708) to the front side of the semiconductor wafer, to the rear side of the semiconductor wafer, to the lateral wall of the trench (Fig. 27), and to the lateral wall of the through hole (fig. 27); removing the insulating layer on a part of a top of the front terminal contact for at least one of the two solar cell stacks (2708 is removed on the top for 2702A’s); and
applying a contact layer (2710/2711/2720) extending from the exposed top of the front terminal contact over the dielectric insulating layer through the trench and the hole to a region of the rear side of the semiconductor wafer adjacent to the hole and coated with the dielectric insulating layer for at least one of the two solar cell stacks (Fig. 27).
Lucow does not explicitly disclose that the trench has an oval perimeter in cross section; the trench extends at least beyond a p-n junction of the Ge subcell at a distance from the front terminal contact for the two solar cell stacks; the hole is a through hole and the insulating layer is applied to the rear side of the semiconductor wafer and to the lateral wall of the through hole.
In an analogous art, Fidaner discloses that the trench has an oval perimeter in cross section (Para 0058 – there can be different shapes); the trench extends at least beyond a p-n junction of the Ge subcell at a distance from the front terminal contact for the two solar cell stacks (Para 0007; 0019 – vias/trenches etched from the top and pass through the epitaxial layers i.e. extends beyond junctions including p-n junctions); the hole is a through hole (Fig. 5A -Para 0025; 0030 – through substrate vias) and the insulating layer (Para 0054 – insulating layer 61&64) is applied to the rear side of the semiconductor wafer (64 of Fig. 5A) and to the lateral wall of the through hole (61 of Fig. 5A). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lucow’s method by having Fidaner’s disclosure in order to connect and adjust different components to optimize the device for absorbing different portions of the solar spectrum to improve the efficiency of solar energy conversion.
With respect to claim 2, Lucow discloses wherein, prior to production of the trench, an antireflection layer (703 of Fig. 7) is applied to a part of the top of the semiconductor wafer that is not covered by the front terminal contacts (Para 0079 – 703 is applied to the top of the wafer not coverd by 702A), and wherein, after the removal of the insulating layer on a part of a top of the front terminal contact, the antireflection layer is removed from the part of the top of the front terminal contact (Fig. 27).
With respect to claim 3, Lucow discloses wherein the dielectric insulating layer is an antireflection layer (2708 of Fig. 27 – Para 0113).
With respect to claim 5, Lucow discloses wherein the front terminal contact is applied via at least one mask process (Para 0007, 0081 &0089).
With respect to claim 6, Lucow discloses wherein the trench is formed by an etching process (Para 0028-0029).
With respect to claim 7, Lucow discloses wherein the etching process for producing the trench comprises two etching steps (Figs. 10A-10B -Para 0028; 0033; etching and subsequent etching).
With respect to claim 10, Lucow disclsoes wherein the Ge substrate is thinned from the rear side of the semiconductor wafer after the production of the trench or after the production of the through hole (Figs. 23-24, Para 0065).
With respect to claim 11, Lucow/Fidaner discloses the method according to claim 1.
Lucow does not explicitly disclose wherein for each of the two solar cell stacks, a rear terminal contact is arranged on the rear side of the semiconductor wafer at a point in time before the application of the dielectric layer, and the dielectric insulating layer on a part of a top of the rear terminal contact is removed at a point in time after the application of the dielectric insulating layer, or
wherein, for each of the two solar cell stacks, the dielectric insulating layer is removed from a section of the surface of the rear side of the semiconductor wafer at a point in time after the application of the dielectric insulating layer, and a rear terminal contact is applied to the exposed surface section of the rear side of the semiconductor.
In an analogous art, Fidaner discloses wherein, for each of the two solar cell stacks, the dielectric insulating layer is removed from a section of the surface of the rear side of the semiconductor wafer at a point in time after the application of the dielectric insulating layer, and a rear terminal contact is applied to the exposed surface section of the rear side of the semiconductor (Para 0054-0057).Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lucow’s method by having Fidaner’s disclosure in order to connect and adjust different components to optimize the device for absorbing different portions of the solar spectrum to improve the efficiency of solar energy conversion.
Claims 4 is rejected under 35 U.S.C. 103 as being unpatentable over
Lucow/Fidaner in view of Komori et al. (US 6,323,416, hereinafter Komori).
With respect to claim 4, Lucow/Fidnar discloses the method of claim 1.
Lucow/Fidnar does not explicitly disclose wherein a first highly doped semiconductor contact layer is applied to the front side of the semiconductor wafer, and a metal layer is applied to a top of the highly doped semiconductor contact layer as the front terminal contact.
In an analogous art, Komori discloses wherein a first highly doped semiconductor contact layer is applied to the front side of the semiconductor wafer (Col. 9, lines 24-45), and a metal layer is applied to a top of the highly doped semiconductor contact layer as the front terminal contact (Col. 9, lines 15-22, and lines 41-50). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lucow/Fidanr’s method by having Komori’s disclosure in order to provide effective current collection to improve the performance of the semiconductor device.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over
Lucow/Fidaner in view of Leitz et al. (US 2010/0270653, hereinafter Leitz).
With respect to claim 8, Lucow/Fidnar does not explicitly disclose wherein the trench is formed by a laser ablation process.
In an analogous art, Leitz discloses wherein the trench is formed by a laser ablation process (Para 0062). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lucow/Fidanr’s method by having Leitz’s disclosure in order to improve the precision and accuracy of the etching process.
With respect to claim 9, Lucow/Fidnar does not explicitly disclose wherein the dielectric insulating layer is removed from the top of the front terminal contact and/or from the bottom of the semiconductor wafer via a laser ablation process or by an etching process.
In an analogous art, Leitz discloses wherein the dielectric insulating layer is removed from the top of the front terminal contact and/or from the bottom of the semiconductor wafer via a laser ablation process or by an etching process (Para 0062 - selective etching). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lucow/Fidanr’s method by having Leitz’s disclosure in order to improve the precision and accuracy of the etching process.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fairbanks Brent can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
Prosecution Insights