Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment filed on 4/22/26 has been entered.
Response to Arguments
Applicant’s arguments with regard to the amendments have been fully considered but they are moot because the arguments do not apply to any of the references being used in the current rejection.
Claim Objections
Claim 3 is objected to because of the following informalities: the “Si3N4” and “SiO2” should be “Si3N4” and “SiO2”.
Claim 7 is objected to because of the following informalities: the “SiH2NH” should be “SiH2NH”.
Claim 12 is objected to because of the following informalities: the “Si3N4” and “SiO2” should be “Si3N4” and “SiO2”.
Claim 15 is objected to because of the following informalities: the “SiO2” and “Si3N4” and should be “SiO2” and “Si3N4”.
Claim 18 is objected to because of the following informalities: the “SiH2NH” should be “SiH2NH”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hung (US 20230135084).
Regarding claim 1. (Currently Amended) Fig 12 of Hung discloses A semiconductor structure, comprising:
a trench (between left 210 in 10 and right 210 in 20) in a substrate 202,
wherein the trench has an opening (top opening filled by 236);
one or more spacers (ridge structures 240, including bottom portions 232 formed from isolation feature 206) at a bottom surface of the trench (Fig 12, [0031]),
wherein the one or more spacers project from the bottom surface of the trench toward the opening of the trench (ridge structures 240 are disposed at the bottom region of the trench and extend upwardly toward the trench opening); and
spin-on dielectric 236 ([0034]: spin-on coating) in the trench.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Hung (US 20230135084) in view of Chung (US 20190164848).
Regarding claim 2. (Original) Hung discloses The semiconductor structure of claim 1. But Hung does not expressly disclose wherein each of the one or more spacers comprises:
a substrate portion at the bottom surface of the trench; a nitride portion on the substrate portion; and an oxide portion on sidewalls and a bottom surface of the nitride portion.
However, Chung discloses protruding semiconductor structures including substrate portions 204, nitride portions 209 disposed on the substrate portions, and oxide regions 208/280 on sidewalls (via 280) and a bottom surface (via 208) of the nitride portion (Fig. 5; [0028], [0043]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the spacer structures of Hung to include the substrate/nitride/oxide arrangement taught by Chung because oxide and nitride layers were conventionally employed in semiconductor isolation structures to provide dielectric isolation, etch selectivity, and structural integrity. Incorporating Chung's known substrate/nitride/oxide configuration into Hung's spacer structures would have predictably yielded spacer structures comprising a substrate portion, a nitride portion on the substrate portion, and oxide material disposed along bottom and sidewall regions of the nitride portion while preserving the trench isolation functions taught by Hung.
Regarding claim 3. (Original) Hung in view of Chung discloses The semiconductor structure of claim 2, Chung teaches pad nitride layer 209 ([0026]: 209 is silicon nitride) and pad oxide layer 208 ([0026]: 209 is silicon oxide) as well as oxide layer 280 ([0028]: 209 is silicon oxide).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize silicon oxide and silicon nitride as the oxide and nitride materials of the pad oxide and pad nitride layers taught by Chung because silicon oxide and silicon nitride were well-known materials conventionally employed for such oxide and nitride layers in semiconductor isolation structures. Chung expressly confirms the conventional use of silicon oxide and silicon nitride in trench isolation structures. The substitution would have yielded predictable results.
Regarding claim 8. (Original) Hung discloses The semiconductor structure of claim 1, Chung teaches further comprising: an oxide ([0028]: 280 is multilayer of silicon oxide layer and silicon nitride layer, thus the bottom layer is the oxide) on the bottom surface of the trench and over the one or more spacers; and
a nitride liner over the oxide ([0028]: 280 is multilayer of silicon oxide layer and silicon nitride layer, thus the upper layer is the nitride liner).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the trench structure of Hung with the oxide and nitride liner arrangement taught by Chung because oxide/nitride liner stacks were conventionally employed in trench isolation structures to provide dielectric isolation, improve etch selectivity, reduce stress, and improve structural integrity of subsequently formed trench-fill structures. Incorporating Chung's oxide and nitride liner arrangement into Hung's trench structure would have predictably yielded an oxide disposed on the bottom surface of the trench and over the spacer structures, and a nitride liner disposed over the oxide.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Hung (US 20230135084) in view of Chung (US 20190164848), and further in view of Fang (US 20170373143).
Regarding claim 4. (Original) Hung in view of Chung discloses The semiconductor structure of claim 2, But Hung in view of Chung does not expressly disclose wherein the trench has a depth of between 300 nm and 400nm, and each of the one or more spacers has a height of between 170 nm and 210 nm.
However, Fang teaches that a trench may have a depth ranging from about 0.3 μm to about 0.5 μm (300 nm to 500 nm) [0021]. Fang further teaches that a raised portion may have a height ranging from about 50 nm to about 250 nm [0036].
The claimed trench depth of between 300 nm and 400 nm overlaps Fang's disclosed trench-depth range of 300 nm to 500 nm. Further, the claimed spacer height of between 170 nm and 210 nm falls within Fang's disclosed raised-portion height range of 50 nm to 250 nm.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select trench depths and spacer heights within the ranges taught by Fang because such dimensions are recognized design parameters of trench isolation structures and protruding semiconductor features. The claimed ranges either overlap or are encompassed by the ranges expressly taught by Fang. It is further noted that the specification contains no disclosure of either the critical nature of instant claimed range or any unexpected results arising thereof. Where patentability is said to be based upon particular chosen values or upon another variable recited in a claim, the applicant must show that the chosen values are critical. In re Woodruff, 919 F.2d 1575, 1578,16 USPQ2d 1934,1936 (Fed Cir.1990). See also, In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Regarding claim 5. (Original) Hung in view of Chung and Fang discloses The semiconductor structure of claim 4. Fang further teaches that a raised portion may have a width ranging from about 50 nm to about 400 nm [0036].
The claimed spacer width of between 40 nm and 60 nm overlaps Fang's disclosed width range of 50 nm to 400 nm.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a spacer width within the overlapping range taught by Fang because spacer width is a recognized dimensional parameter of protruding semiconductor structures and selection of a width within a known overlapping range would have been a matter of routine optimization yielding predictable results. It is further noted that the specification contains no disclosure of either the critical nature of instant claimed range or any unexpected results arising thereof. Where patentability is said to be based upon particular chosen values or upon another variable recited in a claim, the applicant must show that the chosen values are critical. In re Woodruff, 919 F.2d 1575, 1578,16 USPQ2d 1934,1936 (Fed Cir.1990). See also, In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Hung (US 20230135084) in view of Chung (US 20190164848), further in view of Fang (US 20170373143), and further in view of Juengling (US 20140117419).
Regarding claim 6. (Original) Hung in view of Chung and Fang discloses The semiconductor structure of claim 4. Fang teaches raised portions having heights ranging from about 50 nm to about 250 nm [0036]) which is overlapped to the claimed range between 80 nm and 100 nm. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
But Hung in view of Chung and Fang does not expressly disclose the nitride portion has a height of between 80 nm and 100 nm.
However, Juengling further teaches nitride layer 801’ formed over the etched substrate portions 102’ (Fig. 8; ¶[0023]). As shown in Figs. 8 and 9, nitride layer 801 is disposed over etched substrate portion 102', such that the spacer structure includes a substrate portion and a nitride portion corresponding to the claimed configuration. Juengling teaches etching silicon fins 102 to depths ranging from about 500 Å to about 5000 Å (approximately 50 nm to 500 nm) [0021]. Thus, Juengling teaches substrate-portion heights overlapping the claimed range of between 80 nm and 100 nm. Further, the height of nitride layer 801 corresponds to the height of the etched fin structure shown in Figs. 8 and 9 and likewise falls within a dimensional range that overlaps the claimed range of between 80 nm and 100 nm. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select heights for the substrate portion and nitride portion within the overlapping dimensional ranges taught by Juengling because layer height and feature height are recognized result-effective variables affecting device geometry, isolation characteristics, and fabrication requirements. The claimed ranges merely represent selection of values from within known overlapping ranges. Applicant has not identified, and the Specification does not disclose, any criticality or unexpected results associated with selecting heights between 80 nm and 100 nm.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hung (US 20230135084) in view of Chung (US 20190164848), and further in view of Peng (US 20190103276).
Regarding claim 7. (Original) Hung in view of Chung discloses The semiconductor structure of claim 1. But Hung in view of Chung does not expressly disclose wherein the spin-on dielectric comprises perhydrosilazane (SiH2NH).
However, Peng teaches that dielectric material filling trenches may be formed using a spin-on dielectric process and specifically teaches that suitable spin-on dielectric materials include perhydrosilazane (TCPS) [0041].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the perhydrosilazane spin-on dielectric taught by Peng as the spin-on dielectric of Hung in view of Chung because Peng identifies perhydrosilazane as a known suitable spin-on dielectric material for trench-fill dielectric structures, yielding the predictable result of forming the dielectric fill using a recognized alternative spin-on dielectric material.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20120034757) in view of Hung (US 20230135084).
Regarding claim 9. (Currently Amended) Fig 3A of Choi discloses A semiconductor structure, comprising:
a memory cell region ([0064]: area A);
a peripheral region ([0084]: area C);
an isolation region ([0076]: area B) between the memory cell region and the peripheral region,
wherein the isolation region comprises spin-on dielectric 343 filled in a trench in a substrate (same as the 540 and 545 shown in Fig 5F, which are formed by spin-on [0115]/[0123]).
But Choi does not expressly disclose the trench having one or more spacers at a bottom surface of the trench, wherein the one or more spacers project from the bottom surface of the trench toward an opening of the trench.
However, Fig 12 of Hung discloses the trench having one or more spacers at a bottom surface of the trench, wherein the one or more spacers project from the bottom surface of the trench toward an opening of the trench (ridge structures 240 are disposed at the bottom region of the trench and extend upwardly toward the trench opening).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Hung's trench isolation structure into the isolation region of Choi because Hung teaches that such trench structures provide improved dielectric filling characteristics and isolation performance in semiconductor devices. The modification merely involves using a known trench isolation configuration for the known isolation region of Choi to obtain the predictable benefit of improved isolation and gap-fill characteristics.
Regarding claim 10. (Original) Choi in view of Hung discloses The semiconductor structure of claim 9, wherein Choi discloses the memory cell region comprises one or more word lines 315a [0067], and the peripheral region comprises periphery circuits [0086].
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20120034757) in view of Hung (US 20230135084), and further in view of Chung (US 20190164848).
Regarding claim 11. (Original) Choi in view of Hung discloses The semiconductor structure of claim 9. But Choi in view of Hung does not expressly disclose wherein each of the one or more spacers comprises: a substrate portion at the bottom surface of the trench; a nitride portion on the substrate portion; and an oxide portion on sidewalls and a bottom surface of the nitride portion.
However, Fig 5 of Chung discloses a substrate portion 204 at the bottom surface of the trench; a nitride portion 209 [0043] on the substrate portion; and an oxide portion 280/208 [0028]/[0043] on sidewalls (vias 280) and a bottom surface (via 208) of the nitride portion.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the spacers of Hung using the layered spacer structure taught by Chung because Chung teaches that such multilayer spacer configurations provide improved process integration, dielectric isolation, and etch control during semiconductor fabrication. Substituting one known spacer structure for another known spacer structure represents the predictable use of prior-art elements according to their established functions.
Regarding claim 12. (Original) Choi in view of Hung and Chung discloses The semiconductor structure of claim 11, Chung discloses 209 is pad nitride ([0026]: silicon oxide) and 280 is silicon oxide [0028] and 208 is pad oxide ([0026]: silicon oxide).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the specifically disclosed silicon nitride and silicon oxide materials in the spacer structure because these materials were well-known and conventionally used for semiconductor spacer and isolation structures to obtain their known dielectric and etch-selectivity properties.
Claims 13-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20120034757) in view of Fang (US 20170373143).
Regarding claim 13. Choi teaches A method of forming a semiconductor structure comprising:
forming one or more first trenches 531a in a first portion of a substrate 501 and one or more second trenches 531b in a second portion of the substrate (Fig 5A);
forming an oxide layer 535 [0111] on inner walls of the one or more first trenches and the one or more second trenches (Fig 5C);
forming a dielectric layer 540/545 on the oxide layer within to fill the one or more first trenches (Fig 5F); and
forming a shallow trench isolation (STI) trench in the first portion of the substrate, the first portion having the one or more first trenches with the oxide layer and the dielectric layer formed therein (Fig 5F: in B area).
But Choi does not expressly disclose the dielectric layer 140 is a nitride layer.
However, Fang discloses the dielectric layer 140 is a nitride layer ([0025]: silicon nitride).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize Fang's silicon nitride trench-fill material in the trench structures of Choi because Fang teaches that silicon nitride is a suitable dielectric material for STI trench filling. Substituting Fang's known silicon nitride trench-fill material for the insulating fill material of Choi would have merely involved the predictable use of a known dielectric material for its established purpose of electrically isolating adjacent semiconductor regions.
Regarding claim 14. (Original) Choi in view of Fang discloses The method of claim 13, wherein the forming of the STI trench comprises:
a lithography process forming a photoresist having an opening in the first portion of the substrate, the first portion having the one or more first trenches with the oxide layer and the nitride layer formed therein; an etch process etching the first portion of the substrate through the opening (Choi teaches application of photoresist, exposure, development, etching, and photoresist removal to form trenches in the substrate ([0017], [0022]). Choi teaches that the trenches are formed by etching exposed substrate portions through openings defined by the photoresist pattern.
Therefore, Choi teaches: a lithography process forming a photoresist having an opening in the first portion of the substrate; and an etch process etching the first portion of the substrate through the opening).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the conventional lithographic and etching techniques taught by Choi because such techniques represent standard semiconductor fabrication operations for defining trench structures.
Regarding claim 15. (Original) Choi in view of Fang discloses The method of claim 13, Cho discloses wherein the oxide layer comprises silicon oxide (SiO2) [0111], and Fang discloses the nitride layer 140 comprises silicon nitride (Si3N4) [0025].
Regarding claim 16. (Currently Amended) Choi in view of Fang discloses The method of claim 13, Choi discloses further comprising:
forming an oxide on sidewalls and a bottom surface of the STI trench; and forming a nitride liner on the oxide (the 535 is the same as the 335 in Fig 3A; Choi further teaches that trench insulating layer 335 includes silicon oxide and silicon nitride [0094]. The trench insulating layer corresponds to liner structure 535 shown in the process flow of Figs. 5A-5F. Accordingly, Choi teaches an oxide disposed on sidewalls and a bottom surface of the STI trench and a nitride liner disposed on the oxide).
Regarding claim 17. (Original) Choi in view of Fang discloses The method of claim 13, Choi disclose further comprising:
filling the STI trench with spin-on dielectric [0115]; and
densifying the spin-on dielectric within the STI trench [0122].
Regarding claim 19. (Original) Choi in view of Fang discloses The method of claim 17, Choi discloses further comprising:
planarizing the spin-on dielectric with a top surface of the second portion of the substrate (Choi further teaches performing a planarizing process, such as a chemical mechanical polishing (CMP) process or etch-back process, to planarize the trench-fill structure ([0124]). Choi expressly teaches that following the planarization process, trench insulators 540a, 540b/545b, and 540c/545c remain within their respective trenches).
Regarding claim 20. (Currently Amended) Choi in view of Fang discloses The method of claim 13, wherein;
the STI trench 212 has a depth of between 300 nm and 400nm, and a width of between 250 nm and 400 nm, and the one or more first trenches each have a depth of between 200 nm and 270 nm, and a width of between 40 nm and 60 nm (Choi teaches multiple trench populations formed in different substrate regions. Specifically, Choi teaches cell trench 531a having width W5 and depth D5 and teaches core trench 531b having a width equal to or greater than peripheral trench 531c, wherein peripheral trench 531c has width W6 and depth D6, and W6 is greater than W5 and D6 is greater than D5 [0110]. Thus, Choi teaches a first trench population having a smaller width and smaller depth and an STI/core trench population having a larger width and larger depth.
Further, Fang teaches that trench 122 may have a depth ranging from about 0.3 μm to about 0.5 μm (300 nm to 500 nm) [0021]. Fang further teaches raised portions 126 having widths ranging from about 50 nm to about 400 nm and heights ranging from about 50 nm to about 250 nm [0036].
Accordingly, Fang teaches trench-feature dimensions within the same dimensional regime as the claimed trench structures, including dimensions overlapping the claimed STI trench depth of between 300 nm and 400 nm.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select trench widths and depths within the known dimensional ranges taught by Fang while maintaining the larger-width/larger-depth STI trench relationship taught by Choi because trench width and trench depth are recognized result-effective variables affecting isolation performance, device geometry, stress distribution, pattern density, and fabrication characteristics. Choi expressly teaches the same relative dimensional relationship recited in claim 20, namely that the STI/core trench is wider and deeper than the other trench structures. The claimed numerical ranges merely represent optimization of known result-effective variables while preserving the known trench-size relationship taught by Choi).
Further, Applicant has not identified, and the Specification does not disclose, any criticality or unexpected results associated with selecting trench widths and depths within the claimed ranges. Therefore, selection of the claimed dimensions would have been a matter of routine optimization yielding predictable results.
Accordingly, the combination of Choi and Fang renders obvious the subject matter of claim 20.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20120034757) in view of Fang (US 20170373143), and further in view of Peng (US 20190103276).
Regarding claim 18. (Original) Choi in view of Fang discloses The method of claim 17. But Choi in view of Fang discloses does not expressly disclose wherein the spin-on dielectric comprises perhydrosilazane (SiH2NH).
However, Peng teaches that dielectric material filling trenches may be formed using a spin-on dielectric process and specifically teaches that suitable spin-on dielectric materials include perhydrosilazane (TCPS) [0041].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the perhydrosilazane spin-on dielectric taught by Peng as the spin-on dielectric of Choi in view of Fang because Peng identifies perhydrosilazane as a known suitable spin-on dielectric material for trench-fill dielectric structures, yielding the predictable result of forming the dielectric fill using a recognized alternative spin-on dielectric material.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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