Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Abstract
The abstract is objected to because of the following informalities:
Applicant is reminded of the proper language and format for an abstract of the disclosure. The Abstract filed on 12/11/2023 is too short to describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details. The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. See MPEP 608.01(b).
Appropriate correction is required.
Claim Objections
Claim 16 is objected to because of the following informalities: the “a oxide” should be “an oxide”.
Claim 20 is objected to because of the following informalities: the “trench 212” should be “trench [[212]]”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 7-8, 13 and 15-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Peng (US 20190103276).
Regarding claim 1. Fig 1F of Peng discloses A semiconductor structure, comprising:
a trench 114 in a substrate 110 [0017];
one or more spacers 140 [0027] at a bottom surface of the trench; and
spin-on dielectric 150 [0041] in the trench.
Regarding claim 2. Peng discloses The semiconductor structure of claim 1, wherein each of the one or more spacers comprises:
a substrate portion (the portion between 116, below the trench) at the bottom surface of the trench;
a nitride portion 142 [0021] on the substrate portion; and
an oxide portion 144 [0025] on sidewalls and a bottom surface of the nitride portion (Fig 1F).
Regarding claim 3. Peng discloses The semiconductor structure of claim 2, wherein
the nitride portion comprises silicon nitride (Si3N4) ([0021]/[0024]/[0028]: silicon-containing precursors with NH3), and
the oxide portion comprises silicon oxide (SiO2) [0025]/[0029]: silicon-containing precursors with O2).
Regarding claim 7. Peng discloses The semiconductor structure of claim 1, wherein the spin-on dielectric comprises perhydrosilazane (SiH2NH) [0041].
Regarding claim 8. Peng discloses The semiconductor structure of claim 1, further comprising:
an oxide 144 (the topmost 144) on the bottom surface of the trench and over the one or more spacers (Fig 1F: the 144 on the bottom surface area); and
a nitride liner 142 (the topmost 142) over the oxide (Fig 1F).
Regarding claim 13. Peng discloses A method of forming a semiconductor structure comprising:
forming one or more first trenches 114 (left) in a first portion (left side portion of 110 from the center 116) of a substrate 110 and one or more second trenches 114 (right) in a second portion (right side portion of 110 from the center 116) of the substrate;
forming an oxide layer 144 on inner walls of the one or more first trenches and the one or more second trenches (Fig 1D);
forming a nitride layer 142 on the oxide layer within the one or more first trenches (Fig 1D); and
forming a shallow trench isolation (STI) trench in the first portion of the substrate, the first portion having the one or more first trenches with the oxide layer and the nitride layer formed therein (Fig 1G, [0043]).
Regarding claim 15. Peng discloses The method of claim 13, wherein
the oxide layer comprises silicon oxide (SiO2) ([0025]/[0029]: silicon-containing precursors with O2), and
the nitride layer comprises silicon nitride (Si3N4) ([0021]/[0024]/[0028]: silicon-containing precursors with NH3).
Regarding claim 16. Peng discloses The method of claim 13, further comprising:
forming a oxide 144 (the upper 144) on sidewalls and a bottom surface of the STI trench (Fig 1E: the 144 is formed on the bottom surface area of the STI); and
forming a nitride liner 142 (the topmost 142) over the oxide (Fig 1E).
Regarding claim 17. Peng discloses The method of claim 13, further comprising:
filling the STI trench with spin-on dielectric 150 (Fig 1F, [0041]); and
densifying the spin-on dielectric within the STI trench ([0042]: curing process).
Regarding claim 18. Peng discloses The method of claim 17, wherein the spin-on dielectric comprises perhydrosilazane (SiH2NH) [0041].
Regarding claim 19. Peng discloses The method of claim 17, further comprising:
planarizing the spin-on dielectric with a top surface of the second portion of the substrate (Fig 1G, [0043]).
Claims 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nagai (US 20190237469).
Regarding claim 9. Nagai discloses A semiconductor structure, comprising:
a memory cell region 100a (Fig 1, [0020]);
a peripheral region 100c (Fig 1, [0020]);
an isolation region 102 [0021] between the memory cell region and the peripheral region (Fig 1, [0021]), wherein
the isolation region comprises spin-on dielectric filled in a trench [0021] in a substrate 100 (Fig 1),
the trench having one or more spacers at a bottom surface of the trench ([0021]: ‘gap-filling ability to obtain local planarization and form thin dielectric layer. Other oxide layer, nitride layer or liner may be formed around the STI 102’).
Regarding claim 10. Nagai discloses The semiconductor structure of claim 9, wherein
the memory cell region comprises one or more word lines 104 (Fig 1, [0022]), and
the peripheral region comprises periphery circuits ([0021]: register).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Peng (US 20190103276).
Regarding claim 4. Peng discloses The semiconductor structure of claim 2. But Peng does not explicitly disclose wherein the trench has a depth of between 300 nm and 400 nm, and each of the one or more spacers has a height of between 170 nm and 210 nm.
However, the ordinary artisan would have recognized the claimed range to be a result effective variable affecting to make proper STI structure for sub-micron and nanometer-scale devices, primarily by balancing efficient electrical isolation with mechanical stress management. Thus, it would have been obvious that Peng’s dimension within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B
It is further noted that the specification contains no disclosure of either the critical nature of instant claimed range or any unexpected results arising thereof. Where patentability is said to be based upon particular chosen values or upon another variable recited in a claim, the applicant must show that the chosen values are critical. In re Woodruff, 919 F.2d 1575, 1578,16 USPQ2d 1934,1936 (Fed Cir.1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art).
Regarding claim 5. Peng discloses The semiconductor structure of claim 4. But Peng does not explicitly disclose wherein each of the one or more spacers has a width of between 40 nm and 60 nm.
However, the ordinary artisan would have recognized the claimed range to be a result effective variable affecting to make proper STI structure for sub-micron and nanometer-scale devices, primarily by balancing efficient electrical isolation with mechanical stress management. Thus, it would have been obvious that Peng’s dimension within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B
It is further noted that the specification contains no disclosure of either the critical nature of instant claimed range or any unexpected results arising thereof. Where patentability is said to be based upon particular chosen values or upon another variable recited in a claim, the applicant must show that the chosen values are critical. In re Woodruff, 919 F.2d 1575, 1578,16 USPQ2d 1934,1936 (Fed Cir.1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art).
Regarding claim 6. Peng discloses The semiconductor structure of claim 4. But Peng does not explicitly disclose wherein the nitride portion has a height of between 80 nm and 100 nm, and the substrate portion has a height of between 80 nm and 100 nm.
However, the ordinary artisan would have recognized the claimed range to be a result effective variable affecting to make proper STI structure for sub-micron and nanometer-scale devices, primarily by balancing efficient electrical isolation with mechanical stress management. Thus, it would have been obvious that Peng’s dimension within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B
It is further noted that the specification contains no disclosure of either the critical nature of instant claimed range or any unexpected results arising thereof. Where patentability is said to be based upon particular chosen values or upon another variable recited in a claim, the applicant must show that the chosen values are critical. In re Woodruff, 919 F.2d 1575, 1578,16 USPQ2d 1934,1936 (Fed Cir.1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art).
Regarding claim 20. Peng discloses The semiconductor structure of claim 13. But Peng does not explicitly disclose wherein; the STI trench 212 has a depth of between 300 nm and 400 nm, and a width of between 250 nm and 400 nm, and the one or more first trenches each have a depth of between 200 nm and 270 nm, and a width of between 40 nm and 60 nm.
However, the ordinary artisan would have recognized the claimed range to be a result effective variable affecting to make proper STI structure for sub-micron and nanometer-scale devices, primarily by balancing efficient electrical isolation with mechanical stress management. Thus, it would have been obvious that Peng’s dimension within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B
It is further noted that the specification contains no disclosure of either the critical nature of instant claimed range or any unexpected results arising thereof. Where patentability is said to be based upon particular chosen values or upon another variable recited in a claim, the applicant must show that the chosen values are critical. In re Woodruff, 919 F.2d 1575, 1578,16 USPQ2d 1934,1936 (Fed Cir.1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art).
Claims 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Nagai (US 20190237469) in view of Lee (US 20110012226).
Regarding claim 11. Nagai discloses The semiconductor structure of claim 9, wherein each of the one or more spacers comprises:
a substrate portion at the bottom surface of the trench (Fig 1).
But Nagai does not explicitly disclose a nitride portion on the substrate portion; and an oxide portion on sidewalls and a bottom surface of the nitride portion.
However, Fig 2E of Lee discloses a nitride portion 122 [0023] on the substrate portion 110; and an oxide portion 120 [0021] on sidewalls and a bottom surface of the nitride portion.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Nangai’s device structure to have the Lee’s STI structure for the purpose of providing enhanced reliability, stress management, and structural integrity.
Regarding claim 12. Nagai in view of Lee discloses The semiconductor structure of claim 11, Lee discloses wherein
the nitride portion comprises silicon nitride (Si3N4) [0023], and
the oxide portion comprises silicon oxide (SiO2) [0021].
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Nagai (US 20190237469) in view of Ishii (US 5112771).
Regarding claim 14. Peng discloses The method of claim 13. But Peng does not explicitly disclose wherein the forming of the STI trench comprises:
a lithography process forming a photoresist having an opening in the first portion of the substrate, the first portion having the one or more first trenches with the oxide layer and the nitride layer formed therein;
an etch process etching the first portion of the substrate through the opening.
However, Ishii discloses a lithography process forming a photoresist having an opening in the first portion (the portion of 11 below 30) of the substrate 11 (Fig 6C – Fig 6D), the first portion having the one or more first trenches 30 with the oxide layer 41 and the nitride layer 42 formed therein (44 is patterned etch mask which means formed by photolithography, typically by creating a patterned photoresist layer over a silicon dioxide surface, followed by etching to remove exposed oxide and stripping the resist);
an etch process etching the first portion of the substrate through the opening (Fig 6E, col 6, line 44-46).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the Ishii’s method within Peng’s method for the purpose of providing enhanced scalability and planarity Thereby increasing the packing density of components on an integrated circuit and facilitates scaling to deep sub-micron technology.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Changhyun Yi/Primary Examiner, Art Unit 2812