DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 7-12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/2/26.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3 have been considered but are moot because the new ground of rejection relies on a new reference for teaching matters specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, the language “the first via communicates with…, and the second via communicates the… is unclear and --electrically connects-- is definite instead. Also, the phrase “a first and a second elements disposed in…and/or in” is indefinite. Further, the relationship between “a second dielectric layer…” and “a first via penetrating…” versus the “second via” that additionally extends through the semiconductor substrate and into the first dielectric layer is unclear.
Claims 2 and 3 are rejected as being based on claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 is/are, to the extent taught and understood, rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2024/0220696 (Wolpert) in view of U.S. Patent Application Publication No. 2022/0130759 (Huang).
Wolpert discloses
1. (Currently amended) A memory device comprising:
a semiconductor substrate ([0037]) comprising a first surface (frontside) and a second surface (backside) opposite to each other;
a first interconnection structure 134, 136 disposed on the first surface of the semiconductor substrate ([0037]) and comprising a first dielectric layer ([0026]) directly disposed on the first surface (frontside) and first wiring layers 122 disposed in the first dielectric layer ([0026]);
a first and a second elements 112, 114, 116, 118 and 140 disposed in the semiconductor substrate ([0037]) and/or in the first dielectric layer ([0026]);
a second interconnection structure 122 disposed on the first interconnection structure 134, 136; and
a third interconnection structure 102, 103, 105, 108 disposed on the second surface (backside) of the semiconductor substrate ([0037]) and comprising:
a second dielectric layer ([0026], associated with third interconnection structure) directly disposed on the second surface (backside);
a third dielectric layer (surrounding backside third interconnection) disposed on the second dielectric layer ([0026]);
second wiring layers 104 disposed in the third dielectric layer ([0026]);
and
a second via 124/324 penetrating through the second dielectric layer ([0026]) and the semiconductor substrate ([0037]) and extending into the first dielectric layer ([0026]) to electrically connect the second wiring layers 104 to the first wiring layers 122, wherein:
a first electrical connection path 134, 136, 122 electrically connecting the first element or the second element 112, 114, 116, 118 or 140 passes through one of the first wiring layers 122 that is closest to the first and second elements 112, 114, 116, 118 and 140 relative to others of the first wiring layers 122; and
a second electrical connection path (through wiring layer 104) electrically connecting the first element or the second element 112, 114, 116, 118 or 140 passes through one of the second wiring layers 104 that is closest to the first and second elements 112, 114, 116, 118 and 140 relative to others of the second wiring layers 104; and
the second via 124/324 communicates the second electrical connection path (through wiring 104) to the first electrical connection path 134, 136, 122, and wherein the second element 104 is electrically connected to the first element 112, 114, 116, 118 through the first electrical connection path 134, 136, 122, the second via 124/324, the second electrical connection path (through wiring layer 104), and the first via (Chiang).
Wolpert fails to disclose
a first via penetrating through the second dielectric layer and extending into the semiconductor substrate to electrically connect the second wiring layers to the first element;
the first via communicates with the second electrical connection path.
Huang teaches
A memory device comprising:
a first via 282 penetrating through the second dielectric layer 230 and extending into the semiconductor substrate 239 to electrically connect the second wiring layers 406 to the first element 260;
the first via 282 communicates with the second electrical connection path (Wolpert).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a first via to connect the second wiring layer to the first element, communicating with the second electrical path in Wolpert. The motivation would be to move additional signal interconnections to the backside of the transistor structure, which increases available routing tracks and enables higher circuit density as taught by Huang ([0013]-[0017], [0053], [0072]).
Claim(s) 2, 3 is/are, to the extent taught and understood, rejected under 35 U.S.C. 103 as being unpatentable over Wolpert in view of Huang as applied to claim 1 above, and further in view of CN Publication No. 116508148 (Gomes).
The combination of references fails to teach
2. (Currently amended) The memory device of claim 1, wherein the semiconductor substrate comprises a cell region and a peripheral region adjacent to the cell region, and at least one of the first element and the second element is disposed in the peripheral region and is electrically connected to a memory array in the cell region through the first electrical connection path and/or the second electrical connection path.
The combination of references fails to teach
3.(Original) The memory device of claim 2, wherein at least one of the first element and the second element comprises a sense amplifier or a word line driver.
Gomes teaches
A memory device comprising:
wherein the semiconductor substrate 1100 / 1500 comprises a cell region and a peripheral region adjacent to the cell region (DRAM), and at least one of the first element 404-2 and the second element 404-3 is disposed in the peripheral region and is electrically connected to a memory array (DRAM) in the cell region through the first electrical connection path (backside) and/or the second electrical connection path (frontside); and
wherein at least one of the first element 404-2 and the second element comprises a sense amplifier 112 or a word line driver.
It would have been obvious to a person or ordinary skill in the art before the effective filing date of the claimed invention to provide a cell region, a peripheral region, a memory array, and a sense amplifier or word line driver in the modified memory device of Wolpert. The motivation would be these regions and components can be designed to create a functional memory hierarchy where they work together as an interconnected system in order to provide circuitry for controlling and accessing the memory array. They ensure fast, reliable and optimized data storage and performance as taught by Gomes.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Application Publication Nos. 2024/0243038 (Lee) 2021/0305381 (Chiang), TW Publication Nos. 2012/05758 (Oganesian), 2020/42363 (Shih), CN Publication No. 11-4156256 (Zhang), KR Publication No. 2015/0137971 (Tsai), teach a memory device teach a third interconnection structure on the rear side of the substrate so the same circuit elements can connect through both front-side and rear-side wiring paths.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571.272.1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TERESA M. ARROYO/Primary Examiner, Art Unit 2893
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