Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I, Species I (Fig. 1Ib, 1Ic), claims 1-3, 6-16 in the reply filed on 03/04/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 4-5, 17-28 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-3 and 6-16 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 recites in line 10 “a first side surface of the circuit substrate” is indefinite as it is not clear it is the first side surface defined previously or a different side surface? How it is extends from the display region to the lead out wiring region when covered by the sealing layer? Appropriate correction is required.
Claim 3 defines “an optical density value of the sealing layer is greater than or equal to 2” but did not define in the specification what type of material and therefore indefinite and for examination purpose standard epoxy has been considered.
Claim 7 defines “a chip bonding film” but did not define in the specification what type of material and therefore indefinite and for examination purpose standard conductive adhesive has been considered.
Claims 2-3, 6-16 are also rejected being dependent on rejected claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, 13 are rejected under 35 U.S.C. 103 as being obvious over Lee et al (US 2017/0358604 A1) in view of Shao et al (US 2020/0312819 A1).
Regarding claim 1: Lee teaches in Fig. 1-2, 4, 5about a display panel, having a display region and a lead out wiring region adjacent to the display region and comprising:
PNG
media_image1.png
617
865
media_image1.png
Greyscale
PNG
media_image2.png
544
818
media_image2.png
Greyscale
a circuit substrate 110 (Fig. 2), having a top surface, a bottom surface opposite to the top surface, and a first side surface connecting the top surface and the bottom surface, wherein the first side surface extends from the display region to the lead out wiring region (as shown);
a plurality of light-emitting elements 120d, disposed at the display region and located on the circuit substrate (as shown);
an encapsulation layer 130a, disposed at the display region and located on the circuit substrate and between the light-emitting elements (Fig. 1), wherein a first terminal surface of the encapsulation layer is aligned with a first side surface of the circuit substrate; and
a sealing layer, covering the first side surface of the circuit substrate and the first terminal surface of the encapsulation layer.
Lee does not explicitly show wherein a first terminal surface of the encapsulation layer is aligned with a first side surface of the circuit substrate; and
a sealing layer, covering the first side surface of the circuit substrate and the first terminal surface of the encapsulation layer.
However a cross sectional view in B-B’ direction of Lee would show the limitation of wherein a first terminal surface of the encapsulation layer is aligned with a first side surface of the circuit substrate. Shao also teaches in Fig. 5A, 6A wherein a first terminal surface of the encapsulation layer 40a is aligned with a first side surface of the circuit substrate 30a.
PNG
media_image3.png
182
705
media_image3.png
Greyscale
Furthermore Shao teaches in Fig. 11 a sealing layer 90, covering the first side surface of the circuit substrate and the first terminal surface of the encapsulation layer.
Therefore it would have been obvious to one of ordinary skill in the art, at the time of applicant was filed to combine Shao’s teachings to Lee’s semiconductor device to use a sealing layer to cover the packages of Lee’s device to protect from external environment.
Regarding claim 2: Lee teaches in Fig. 1, [0026] wherein a height of the encapsulation layer H1 is less than or equal to a height of the light-emitting elements H2.
Regarding claim 3: Lee in view of Shao teaches wherein a thickness of the encapsulation layer is 5 µm to 10 µm [0027], an optical density value of the encapsulation layer is greater than or equal to 3 [0028], and an optical density value of the sealing layer is greater than or equal to 2 (Shao teaches epoxy to form the sealing layer 90 which would have the claimed optical density).
Regarding claim 6: Shao teaches wherein the sealing layer extends from one portion of the first side surface of the circuit substrate located in the display region to the other portion of the first side surface of the circuit substrate located in the lead out wiring region (would be obvious to see in top view).
Regarding claim 13: Lee teaches in Fig. 1 further comprising an optical layer 150 disposed at the display region and located on the light-emitting elements and the encapsulation layer.
Claim 7 is rejected under 35 U.S.C. 103 as being obvious over Lee et al (US 2017/0358604 A1) in view of Shao et al (US 2020/0312819 A1) and further in view of He et al. (US 2018/0122996 A1)
Regarding claim 7: Lee in view of Shao does not talk about further comprising a chip bonding film disposed at the lead out wiring region and electrically connected to the circuit substrate.
He teaches in Fig. 1 about a chip bonding film 5 disposed at the lead out wiring region and electrically connected to the circuit substrate 14.
Therefore it would have been obvious to one of ordinary skill in the art, at the time of applicant was filed to combine He’s teachings to Lee’s semiconductor device to have a better connection between the pad the substrate.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The limitation allowable is “a protection adhesive located in the lead out wiring region and covering the chip bonding film” in combination with other limitations as a whole.
Claims 9-12 are also allowable being dependent on allowable claim 8.
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The limitation allowable is “wherein a first edge surface of the optical layer extends beyond the first terminal surface of the encapsulation layer, and the sealing layer physically contacts the encapsulation layer and the optical layer” in combination with other limitations as a whole.
Claims 15-16 are also allowable being dependent on allowable claim 14.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAMSUZZAMAN whose telephone number is (571)270-1839. The examiner can normally be reached Monday-Friday 7 am -4 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Mohammed Shamsuzzaman/Primary Examiner, Art Unit 2897
Prosecution Insights