Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10, 12-15, and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2022/0085028).
Regarding claim 10, Kim discloses a semiconductor memory device, comprising:
an active pattern (AR) on a substrate (100) and at least partially surrounded by a device isolation pattern (105) [Figs. 1 and 5];
a bit line (133/135) that extends on a center portion (135/136t) of the active pattern (AR) in a first direction (DR3) that is parallel to a bottom surface of the substrate (100) [Fig. 1]; and
a bit line contact (132/136) between the bit line (133) and the active pattern (AR/100) [Figs. 1 and 5],
the bit line contact (132/136) comprising a metallic material [paragraphs 0043-0044],
wherein the bit line contact (132/136) comprises an upper portion (132) and a lower portion (136), wherein the upper portion (132) and the lower portion (136) contact each other at a first level [Fig. 5],
wherein a width of the upper portion (132) at the first level and in a second direction (DR2) is greater than a width of the lower portion (136) at the first level and in the second direction (DR2) [Figs. 1 and 5],
wherein the second direction (DR2) intersects the first direction (DR3) [Fig. 1].
Regarding claim 12, Kim discloses a lower spacer (150_1) on a side surface of the lower portion (136) of the bit line contact, wherein the lower spacer (150_1) is between a top surface of the device isolation pattern (105) and the substrate (100) [Fig. 5].
Regarding claim 13, Kim discloses wherein a width of the lower spacer (152) in the second direction (DR2) decreases toward the substrate (100) [Fig. 5].
Regarding claim 14, Kim discloses wherein a top surface of the lower spacer (151) contacts a bottom surface of the upper portion (132) of the bit line contact (132/136) [Fig. 5].
Regarding claim 15, Kim discloses wherein a bottom surface of the upper portion (132) of the bit line contact covers a portion of a top surface of the lower spacer (151) [Fig. 5].
Regarding claim 17, Kim discloses a semiconductor memory device, comprising:
an active pattern (AR) on a substrate (100) and at least partially surrounded by a device isolation pattern (105) [Figs. 1-5];
a bit line (133/135) that extends on a center portion of the active pattern (AR) in a first direction (DR3) that is parallel to a bottom surface of the substrate (100) [Fig. 1]; and
a bit line contact (132/136) between the bit line and the active pattern [Figs. 1 and 5],
wherein the bit line contact (132/136) comprises a metallic material [paragraphs 0043-0044],
wherein a width of the bit line contact (132/136) at a first level (132) and in a second direction (DR2) is greater than a width of a bottom surface (interface between 136 and 100) of the bit line contact (132/136) in the second direction (DR2) and a width of a top surface (interface between 136 and 132) of the bit line contact (132/136) in the second direction [Fig. 5],
wherein the second direction (DR2) intersects the first direction (DR3) [Fig. 1].
Regarding claim 18, Kim discloses wherein the width of the bit line contact at the first level (132) and in the second direction (DR2) is greater than a width of a top surface (interface 136 and 132) of the bit line in the second direction [Fig. 5].
Regarding claim 19, Kim discloses a lower spacer (151/152) below the first level (132) and on a portion of a side surface of the bit line contact (132/136) [Fig. 5]; and
a lower insulating pattern (154) above the first level (132) and on another portion of the side surface of the bit line contact [Fig. 5].
Allowable Subject Matter
Claims 1-9 are allowed.
Claims 11, 16 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Shin et al. (US 7728375) teaches a bit line BL in Figure 1 and 2A.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday.
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/Jose R Diaz/ Primary Examiner, Art Unit 2815
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