DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-7 in the reply filed on 4/3/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Objections
Claim 1 is objected to because of the following informalities: the phrase, “semiconductor substrate” should be “the semiconductor substrate”. Also, the spacing of the lines in claim 7 is not the same as the rest of the claims’. The formation of claims/claim language is poorly constructed. Appropriate correction is required. Check all of the claims for the similar issue.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Su et al. (US 2021/0351079, hereinafter, Su.)
Regarding claims 1-2 and 7, in fig. 2, Su discloses a method of fabricating a semiconductor device 100 (para [0027]), the method comprising:
forming a deep nanosheet trench between first and second nanosheet stacks formed on a frontside of the semiconductor substrate;
depositing a deep trench liner 118/127 on sidewalls and a bottom end of the deep nanosheet trench, see also figs. 3-4;
forming a source/drain at the 106 region in the deep nanosheet trench (para [0026]);
etching a backside of the semiconductor substrate to form a backside contact trench which exposes the deep nanosheet trench while the deep trench liner prevents etching of the source/drain (fig. 2 showed the finished structure where the backside was edged to form the source/drain contact 120, thus, exposing the source/drain for contact; see also para [0024]);
etching the bottom end of the deep nanosheet trench to expose a bottom end of the source/drain; and
forming a backside contact 122 (para [0024]) in the backside contact trench to establish physical contact between the backside contact and the bottom end of the source/drain.
Regarding claim 2, wherein forming the source/drain comprises:
etching the deep trench liner located at the bottom end of the deep nanosheet trench to form an opening which exposes a portion of semiconductor substrate, fig. 2;
forming a source/drain seed layer on the exposed portion of the semiconductor substrate; and
epitaxially growing the source/drain from the source/drain seed layer, in the region 106, see the description in para [0025].)
Regarding claim 7, Su further comprising:
forming a backside power rail, or metal lines, 216 (para [0024]) on the backside of the semiconductor substrate such that a first surface contacts the backside contact;
forming a backside power distribution network, or interconnect structure, 114 (para [0023])on a second surface of the backside power rail opposite the first surface.
Allowable Subject Matter
Claims 3-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art do not show wherein etching a backside of the semiconductor substrate comprises:
replacing a portion of semiconductor material with a backside interlayer dielectric (ILD);
performing an etching process that is selective to material of the ILD and the source/drain while the deep trench liner prevents etching of sidewalls of the source/drain and the source/drain seed layer prevents etching of the bottom end of the source/drain.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN W HA whose telephone number is (571)272-1707. The examiner can normally be reached M-T: 8:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WAEL FAHMY can be reached at (571)-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NATHAN W HA/Primary Examiner, Art Unit 2814
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