DETAILED ACTION
This Office Action is in response to Applicant’s Election dated 4/14/26.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention. Applicant timely traversed the restriction (election) requirement in the reply filed on 4/14/2026.
Applicant's election with traverse of claims 1-17 in the reply filed on 4/14/2026 is acknowledged. The traversal is on the ground(s) that “the Office has failed to articulate sufficient to demonstrate that the alleged groups are independent or distinct”. This is not found persuasive because, as being mention in the previous Office Action, Inventions I and II are distinct if either or both of the following can be shown: (1) that the process as claimed can be used to make another and materially different product or (2) that the product as claimed can be made by another and materially different process (MPEP § 806.05(f)). Since process invention I can be used to make another and materially different product, for example, a semiconductor structure comprising bit lines wherein a thickness of the bit lines being not uniform in the first direction (process claim 1) while product invention II recites “a thickness of the bit lines being uniform in the first direction” (product claim 18). Process invention I and Product invention II are distinct. The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being being anticipated by Shao et al [CN-114864504]
► With respect to claim 1, Shao et al (figs 1-26, text pages 1-12, see attached translation) discloses the claimed method of forming semiconductor structure comprising:
forming a substrate (100, fig 2), and forming active regions (110, fig 5) located above the substrate and arranged at intervals in a first direction (X direction) parallel to a top face of the substrate; and
performing a modifying treatment to a part of the substrate below the active regions from at least one side face of the substrate, to form bit lines (120, figs 9/10//1) each of which extends in the first direction (X direction) and is electrically connected with a plurality of the active regions (channels 110 in active region 111)) arranged at intervals in the first direction (X direction).
► With respect to claim 2, Shao et al discloses wherein the forming the substrate and forming the active regions located above the substrate and arranged at intervals in the first direction comprises: providing an initial substrate (fig 2); and etching the initial substrate to form first trenches arranged at intervals in the first direction (X direction, figs 3/1), wherein parts of the initial substrate remaining between adjacent first trenches forms the active regions (111 thus 110), and a part of the initial substrate remaining below the first trenches and the active regions forms the substrate (100).
► With respect to claim 3, Shao et al discloses wherein the forming the first trenches arranged at intervals in the first direction (X direction) comprises: etching the initial substrate (100, fig 3) to form second trenches arranged at intervals in a second direction (Y direction) parallel to the top face of the substrate, wherein a part of the initial substrate remaining between adjacent second trenches forms a semiconductor layer (111), a part of the initial substrate remaining below the second trenches and the semiconductor layer forms the substrate (100), wherein the second direction, the first direction (X direction) intersects with the second direction; forming isolation layers (161, fig 4) in the second trenches; and etching the semiconductor layer and the isolation layers to form the first trenches arranged at intervals in the first direction (X direction, fig 5), wherein parts of the semiconductor layer remaining between adjacent first trenches form the active regions (110).
► With respect to claim 4, Shao et al discloses wherein before the performing the modifying treatment to the part of the substrate below the active regions from at least one side face of the substrate, the method further comprises: forming a first protection layer (170, fig 6) covering side walls of parts of the first trenches in the semiconductor layer.
► With respect to claim 5, Shao et al discloses wherein the performing the modifying treatment to the part of the substrate below the active regions from at least one side face of the substrate comprises: performing the modifying treatment to the part of the substrate below the active regions in the second direction.
► With respect to claim 6, Shao et al (fig 7) discloses wherein the performing the modifying treatment to the part of the substrate below the active regions in the second direction comprises: performing the modifying treatment to the part of the substrate below the active regions simultaneously from two side faces of the substrate opposite to each other in the second direction.
Allowable Subject Matter
Claims 7-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANHHA S PHAM whose telephone number is (571)272-1696. The examiner can normally be reached Monday-Friday.
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/THANHHA S PHAM/Primary Examiner, Art Unit 2812
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