DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested: “SEMICONDUCTOR DEVICE HAVING A CHIP GURAD STRUCTURE SURROUNDING A CHIP REGION AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE.”
If Applicant does not agree with the suggested title above, Applicant must provide a new title that clearly reflects the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 10, 12-14 and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US Pub. 2022/0165748).
Regarding Claim 1, Kim discloses a semiconductor device comprising: a stack including a chip region CER and a guard region CGR (page 2, paragraph 30; see figs. 1B and 1C) surrounding the chip region CER (see fig. 1A); contact structures (BCT, BL) positioned in the chip region CER (page 4, paragraph 52; see fig. 1B); and a chip guard structure (GP1, GP2, UG1, UG2) (see fig. 1E) positioned in the guard region CGR (see fig. 1C) and including first protrusions (an upper chip guard UG1, UG2 protrusion) protruding by a first width (a width by a first direction D1; see fig. 1E) and second protrusions (first and second cell guard parts GP1, GP2 protrusion) protruding by a second width (a width by the first direction D1; see fig. 1E) greater than the first width (see figs. 1C and 1E).
Regarding Claim 2, Kim discloses wherein in a plan view, the chip guard structure (GP1, GP2, UG1, UG2) has a ring shape (see fig. 1A).
Regarding Claim 3, Kim discloses wherein an upper surface of the contact structures (BCT, BL) is positioned at the same level as an upper surface (upper surface of the upper chip guard UG1, UG2) of the chip guard structure (GP1, GP2, UG1, UG2) (see figs. 1B and 1C).
Regarding Claim 4, Kim discloses wherein the contact structures (BCT, BL) (page 4, paragraph 52) and the chip guard structure (GP1, GP2, UG1, UG2) include the same material (tungsten; page 6, paragraph 76; page 7, paragraphs 82 and 87).
Regarding Claim 5, Kim discloses wherein the contact structures (BCT, BL) and the chip guard structure (GP1, GP2, UG1, UG2) include at least one of titanium nitride, tungsten, and molybdenum (tungsten; page 4, paragraph 52; page 6, paragraph 76; page 7, paragraphs 82 and 87).
Regarding Claim 6, Kim discloses wherein the contact structures (BCT, BL) and the chip guard structure (GP1, GP2, UG1, UG2) include an insulating material 120 (page 4, paragraph 51; see figs. 1B and 1C).
Regarding Claim 7, Kim discloses further comprising: channel structures CPL (cell plugs CPL including a cell channel layer CCL; page 3, paragraph 45) positioned in the chip region CER (see fig. 1B).
Regarding Claim 10, Kim discloses a method of manufacturing a semiconductor device, the method comprising: forming a stack including a chip region CER and a guard region CGR (page 2, paragraph 30; see figs. 6B and 6C) surrounding the chip region CER (see fig. 6A); forming first openings CHO1 (pages 7-8, paragraph 97) extending through the chip region CER of the stack (see figs. 2A and 6B); forming second openings GHO (first left one) and third openings GHO (second left one) (page 9, paragraph 124) extending through the guard region CGR of the stack and spaced apart from each other (see fig. 7); forming a fourth opening GT (page 9, paragraph 126) by connecting the second openings GHO (first left one) and the third openings GHO (second left one) (page 9, paragraph 126; see fig. 8); forming contact structures CPL in the first openings CHO1 (page 8, paragraph 100; see figs. 4 and 6B); and forming a chip guard structure GP in the fourth opening GT (page 9, paragraph 127; see fig. 9).
Regarding Claim 12, Kim discloses wherein the chip guard structure GP is formed when forming the contact structures CPL (page 8, paragraph 106).
Regarding Claim 13, Kim discloses wherein the second openings GHO and the third openings GHO are formed when forming the first openings CHO1 (page 9, paragraph 124).
Regarding Claim 14, Kim discloses further comprising: forming fifth openings CHO2 (page 8, paragraph 99) extending through the chip region CER (see figs. 3A and 6B); and forming channel structures CPL (cell plugs CPL including a cell channel layer CCL; page 3, paragraph 45) in the fifth openings CHO2 (see figs. 4 and 6B).
Regarding Claim 23, Kim discloses a semiconductor device comprising: a stack including a chip region CER and a guard region CGR (page 2, paragraph 30; see figs. 6B and 6C) surrounding the chip region CER (see fig. 6A); contact structures (BCT, BL) (page 4, paragraph 52) positioned in the chip region CER (see fig. 6B); and a chip guard structure (GPL, GP, UG1, UG2) (see fig. 6D) positioned in the guard region CGR (see fig. 6C), the chip guard structure (GPL, GP, UG1, UG2) having a rectangular ring shape cross-section (see fig. 6A), with sides comprising consecutive concave shape protrusions (the outer and inner sides of the chip guard structure include consecutively arranged circular guard plugs GPL, thereby forming consecutive concave-shaped protrusions; see fig. 6A).
Allowable Subject Matter
Claims 8, 9, 11, 15-22, 24 and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 8 recites supports disposed in the chip region and arranged around the contact structures in a first direction and in a second direction crossing the first direction.
Claim 11 recites each of the first openings is extended when forming the fourth opening.
Claim 15 recites forming a mask pattern covering the channel structures and exposing the first openings, the second openings, and the third openings, wherein the first openings, the second openings, and the third openings are selectively extended by using the mask pattern.
Claim 16 recites the first openings, the second openings, and the third openings are formed when forming the fifth openings.
Claim 17 recites forming sixth openings extending through the chip region; and forming supports in the sixth openings.
Claim 20 recites a width of the third openings is greater than a width of the second openings.
Claim 21 recites the second openings have a circular shape, and the third openings have an elliptical shape.
Claim 22 recites the second openings are arranged in a first direction, and the third openings are arranged in a second direction crossing the first direction.
Claim 24 recites the consecutive concave shape protrusions comprise first protrusions of a first width and second protrusions of a second width, and wherein the second width is greater than the first width.
These features in combination with the other elements of the base claim are neither disclosed nor suggested by the prior art of record.
Claims 9, 18, 19 and 25 variously depend from claim 8, 17 or 24, so they are objected for the same reason.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEUNG LEE whose telephone number is (571)272-5977. The examiner can normally be reached 9 AM - 5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHEUNG LEE/Primary Examiner, Art Unit 2812 May 11, 2026
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