DETAILED ACTION
This correspondence is in response to the communications received December 12, 2023. Claims 1-9 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The disclosure is objected to because of the following informalities: The term “heavy hydrogen” is used throughout the specification. However the more commonly used term for this material is “deuterium” or “hydrogen-2”. Conversely, “heavy hydrogen” also is a umbrella term of “tritium”, which is not supported, and assumed not to be considered as material for use by Applicant. It would appear to be helpful both for Applicant and the public to be able to identify just what is the advantage of this disclosure and to locate this content in the future. Inclusion of these terms as identifying the basic fundamental aspect of this Application seems to be important and currently lacking. Appropriate correction is required.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Fig. 5, 7, 9 and 20, a semiconductor storage element comprising:
a laminated body (S2) in which insulating layers (14) and conductive layers (6) are alternately laminated in a first direction (vertical);
a semiconductor layer (2) disposed in the first direction (vertical) in the laminated body (in S2);
a first insulator (3) disposed in the first direction between the laminated body (S2) and the semiconductor layer (2);
a second insulator (4) disposed in the first direction between the laminated body (S2) and the first insulator (3);
a third insulator (5a) disposed in the first direction between the laminated body (S2) and the second insulator (4); and
a fourth insulator (5b) including a first part (vertical part) and a second part (laterally oriented part), the first part being disposed between each of the conductive layers (6) and the third insulator (5a), the second part being (laterally oriented part) disposed in a second direction (horizontally) intersecting the first direction (vertical) between each of the conductive layers (6) and the insulating layer (14) and connected to the first part (lateral part of 5b is connected to the vertical part of 5b), wherein
the average concentration of heavy hydrogen in the first part is higher than the average concentration of heavy hydrogen in the third insulator (“the average concentration of heavy hydrogen (D) in the insulator 5b is higher than the average concentration of heavy hydrogen (D) in the insulator 5a”, ¶ 0027), and
the ratio of heavy hydrogen concentration to light hydrogen concentration in the first part is smaller than the ratio of heavy hydrogen concentration to light hydrogen concentration in the third insulator (“FIG. 9 illustrates distribution of the concentration ratio of the concentration of heavy hydrogen (D) to the concentration of light hydrogen (H).”, ¶ 0029).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Niguchi (US 2022/0302139) in view of Li et al. (CN 116487331 A).
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Regarding claim 7, the prior art of Niguchi discloses in Figs. 1-5 and 7-9, a semiconductor storage element manufacturing method (“The semiconductor device in FIG. 1 includes … a charge storage film 4”, ¶ 0031) comprising:
sequentially forming a first insulator (“tunnel insulating film 3 is, for example, a SiON film (silicon oxynitride film)”, ¶ 0034), a second insulator (“charge storage film 4 is, for example, a SiN film (silicon nitride film)”, ¶ 0034), a third insulator (“insulating film 5a is, for example, a SiO film (silicon oxide film)”, ¶ 0034), and a semiconductor layer (“channel semiconductor layer 2 is, for example, a polysilicon layer.”, ¶ 0034), which extend in a first direction (extend vertically), in a second direction (horizontal direction) intersecting the first direction in a laminated body (“stacked film S2”, ¶ 0046) in which sacrifice layers (“sacrifice layers 13 are, for example, silicon nitride films (SiN)”, ¶ 0037) and insulating layers (“insulating layers 14 are, for example, silicon oxide films (SiO)”, ¶ 0037) are alternately laminated in the first direction (alternately stacked in a vertical direction);
removing the sacrifice layer (in the sequence steps from Fig. 3 to 4, layer 13 is removed) and forming a fourth insulator on a surface of a region from which the insulating layer is removed (in the sequence steps from Fig. 4 to 5, “insulating film 5b”, ¶ 0031, is formed in the “hollows H2”, ¶ 0040); and
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performing spike annealing treatment for a holding time of five seconds or shorter at a treatment temperature of 1000°C or higher by using heavy hydrogen (D2) gas and heavy water (D2O) to introduce heavy hydrogen (D) into the first insulator, the second insulator, the third insulator, and the fourth insulator (Fig. 9 shows both D2O and D2 treatment into all of layers 5b, 5a, 4 and 3, where ¶ 0058 discloses the RTP or “rapid thermal processing”, which is a different name for “spike annealing”, spike being the short thermal impulse event, and the 1000 degrees Celsius is shown in ¶ 0058 range).
Niguchi does not disclose the thermal annealing type of “spike annealing”, but an annealing method which is equivalently rapid and high temperature.
Li discloses, “In order to further improve the performance of the semiconductor device, in the prior art, after forming the metal gate structure, the device is subjected to a high temperature annealing treatment, such as a spike annealing at 1000 ° C, which can reduce the defects of the metal gate.” (pg. 7, first paragraph, last sentence).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the spike annealing method, as disclosed by Li in the system of Niguchi, for the purpose of reducing the defects of the metal gate among other advantages. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 8, the prior art of Niguchi et al. disclose the semiconductor storage element manufacturing method according to claim 7, wherein the treatment temperature of the spike annealing treatment is higher than a treatment temperature in a manufacturing process later than the spike annealing treatment (selection of higher temp from range in ¶ 0058, and selecting lower temp from range in subsequent step detailed in ¶ 0059).
Regarding claim 9, the prior art of Niguchi et al. disclose the semiconductor storage element manufacturing method according to claim 7, wherein carrier gas of heavy water (D2O) in the spike annealing treatment contains argon (Ar) or nitrogen (N2) (Niguchi discloses the treatment step utilizing, ¶ 0052, “At this time, the pressure in a chamber may be controlled using nitrogen (N.sub.2).”).
REASONS FOR ALLOWANCE
Claims 1-6 are allowed.
The following is an Examiner's statement of reasons for allowance: The a semiconductor storage element as recited in the claims of the instant invention fail to be taught by the prior art cited of interest.
Regarding claim 1, the prior art of Niguchi et al. (US 2022/0302139) discloses a semiconductor storage element, but fails to disclose the specific characteristic recited in the claims of the instant invention as detailed below in the attempt to reject claim 1 with the Niguchi reference.
Regarding claim 1, the prior art of Niguchi discloses in Figs. 1 and 5-8, a semiconductor storage element (“The semiconductor device in FIG. 1 includes … a charge storage film 4”, ¶ 0031) comprising:
a laminated body (“stacked film S2”, ¶ 0046) in which insulating layers (“insulating layers 14”, ¶ 0046) and conductive layers (“electrode layers 6”, ¶ 0046) are alternately laminated in a first direction (alternately stacked in a vertical direction);
a semiconductor layer (“channel semiconductor layer 2 is, for example, a polysilicon layer.”, ¶ 0034) disposed in the first direction (extending vertically) in the laminated body (in S2);
a first insulator (“tunnel insulating film 3 is, for example, a SiON film (silicon oxynitride film)”, ¶ 0034) disposed in the first direction (extending vertically) in the laminated body (in S2) and the semiconductor layer (2);
a second insulator (“charge storage film 4 is, for example, a SiN film (silicon nitride film)”, ¶ 0034) disposed in the first direction (extending vertically) in the laminated body (in S2) and the first insulator (3);
a third insulator (“insulating film 5a is, for example, a SiO film (silicon oxide film)”, ¶ 0034) disposed in the first direction (extending vertically) in the laminated body (in S2) and the second insulator (4); and
a fourth insulator (“insulating film 5b is, for example, a metal insulating film of aluminum oxide”, ¶ 0035) including a first part (vertical portion of 5b) and a second part (horizontal portion of 5b), the first part being (vertical portion of 5b) disposed between each of the conductive layers (6) and the third insulator (5a), the second part (horizontal portion of 5b) being disposed in a second direction intersecting the first direction (horizontal orientation) between each of the conductive layers (6) and the insulating layer (14) and connected to the first part (the horizontal portion of 5b is connected to the vertical portion of 5b).
Niguchi however fails to disclose the following limitations,
“the average concentration of heavy hydrogen in the first part is higher than the average concentration of heavy hydrogen in the third insulator (the average concentration of heavy hydrogen in the vertical portion of 5b is higher than the average concentration of heavy hydrogen in 5a, which is evident in Fig. 7, where “D CONCENTRATION”, which means “deuterium”, which is the alternative name to “heavy hydrogen”, and so “BLKAlO5b” is clearly not greater than “BLK-SiO5a”), and
the ratio of heavy hydrogen concentration to light hydrogen concentration in the first part is smaller than the ratio of heavy hydrogen concentration to light hydrogen concentration in the third insulator (this aspect not taught by Niguchi).”
Regarding claim 6, the prior art of Niguchi (US 2022/0302139) discloses a semiconductor storage element, but fails to disclose the specific characteristic recited in the claims of the instant invention e.g. the combination of claimed features of laminated body, insulating layers, conductive layers, semiconductor layer, first insulator, second insulator, third insulator, fourth insulator including first part and second part, and the relative orientation of each feature with respect to each other, in conjunction with the limitations of,
“the first part includes a High-k film, and
the ratio of heavy hydrogen concentration to light hydrogen concentration in the High-k film is equal to or larger than 10.”
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893