DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 07/14/2026. Claims 1-20 are pending for this examination.
Oath/Declaration
The oath or declaration filed on 12/12/2023 is acceptable.
Election/Restrictions
Applicant’s election, without traverse, species VI (Fig 4) of claims 1-4 and 7-20, in the “Response to Election / Restriction Filed” filed on 07/14/2026 is acknowledged. This office action considers claims 1-20 are thus pending for prosecution of which, non-elected claims 5-6 are withdrawn, and elected claims 1-4 and 7-20 are examined on their merits.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation “a via connecting the uppermost interconnect wiring level to at least one other remaining interconnect wiring level of the at least three interconnect wiring levels, wherein the at least one other remaining interconnect wiring level is stacked over the lowermost interconnect wiring level and wires of the at least one other remaining interconnect wiring level have a minimum pitch which is the same as the minimum pitch of the wires of the lowermost interconnect wiring level” as recites in claim 20, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding Claim 20, The instant claims recite limitation “wires of the at least one other remaining interconnect wiring level have a minimum pitch which is the same as the minimum pitch of the wires of the lowermost interconnect wiring level” is not clear because claim 18 recites “wires of the at least one other remaining interconnect wiring level have a minimum pitch which is the same as the minimum pitch of the wires of the lowermost interconnect wiring level”. Is there multiple minimum pitch for the one other remaining interconnect wiring level, is not clear. In addition, “a minimum pitch which is the same as the minimum pitch of the wires of the lowermost interconnect wiring level” has lack of antecedent issue. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-11 and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by KUROKAWA et al (US 2026/0255633 A1; hereafter KUROKAWA).
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Regarding claim 1. KUROKAWA discloses a semiconductor structure (Fig 17) comprising:
a first device layer (700 [1] includes memory cell MC, Para [ 0321]);
a second device layer (700 [3] includes memory cell MC, Para [ 0321]); and
a plurality of interconnect wiring levels (Fig 17, annotated plurality wiring level, Para [0311-0333]) between the first device layer (700 [1]) and the second device layer (700 [3]), wherein the plurality of interconnect wiring levels (Fig 17, annotated plurality wiring level, Para [0311-0333]) comprise:
a first interconnect wiring level (annotated lower arrow, Para [0311-0333]) adjacent the first device layer (700 [1], Para [0311-0333]), wherein wires of the first interconnect wiring level (Fig 17, annotated lower arrow, Para [ 0311-0333]) are spaced apart from each other at a first pitch (Fig 17, annotated lower arrow, Para [ 0311-0333]);
a second interconnect wiring level (Fig 17, annotated upper arrow, Para [ 0311-0333]) adjacent the second device layer (700 [3], Para [ 0311-0333]), wherein wires of the second interconnect wiring level (Fig 17, annotated upper arrow, Para [ 0311-0333]) are spaced apart from each other at a second pitch (Fig 17, annotated upper arrow, Para [ 0311-0333]); and
at least a third interconnect wiring level (Fig 17, annotated middle arrow, Para [ 0311-0333]) between the first interconnect wiring level (annotated lower arrow) and the second interconnect wiring level (Fig 17, upper arrow, Para [ 0311-0333]), wherein wires of the third interconnect wiring level (Fig 17, annotated middle arrow, Para [ 0311-0333]) are spaced apart from each other at a third pitch (Fig 17, annotated middle arrow, Para [ 0311-0333]), and the third pitch (Fig 17, annotated middle arrow, Para [ 0311-0333]) is greater than the first pitch (Fig 17, annotated lower arrow, Para [ 0311-0333]) and the second pitch (Fig 17, annotated upper arrow, Para [ 0311-0333]).
Regarding claim 2. KUROKAWA discloses the semiconductor structure of claim 1, KUROKAWA further discloses wherein the second device layer (700 [3] includes memory cell MC, Para [0321]) is stacked above the first device layer (700 [1] includes memory cell MC, Para [0321]).
Regarding claim 3. KUROKAWA discloses the semiconductor structure of claim 1, KUROKAWA further discloses further comprising:
a backside back-end-of-line metallization structure (element layer 701, Para [ 0310-0315]) under the first device layer (700 [1] includes memory cell MC, Para [0321]); and a frontside back-end-of-line metallization (annotated front side structure) structure over the second device layer (700 [3] includes memory cell MC, Para [0321]).
Regarding claim 4. KUROKAWA discloses the semiconductor structure of claim 1, KUROKAWA further discloses wherein the first pitch (annotated lower arrow) is the same as the second pitch (Fig 17, annotated upper arrow, Para [0311-0333]).
Regarding claim 7. KUROKAWA discloses the semiconductor structure of claim 1, KUROKAWA further discloses further comprising a via (annotated via right side) connecting the second device layer (700 [3] includes memory cell MC, Para [0321]) to the third interconnect wiring level (Fig 17, annotated middle arrow, Para [0311-0333]).
Regarding claim 8. KUROKAWA discloses the semiconductor structure of claim 1, KUROKAWA further discloses further comprising a via (annotated via right side) connecting the second device layer (700 [3] includes memory cell MC, Para [0321]) to the second interconnect wiring level (Fig 17, annotated upper arrow, Para [0311-0333]).
Regarding claim 9. KUROKAWA discloses the semiconductor structure of claim 1, KUROKAWA further discloses further comprising a via (annotated via right side) connecting the second interconnect wiring level (Fig 17, annotated upper arrow, Para [0311-0333]) to the first interconnect wiring level (annotated lower arrow, Para [0311-0333]).
Regarding claim 10. KUROKAWA discloses the semiconductor structure of claim 1, KUROKAWA further discloses wherein the plurality of interconnect wiring levels (Fig 17, annotated plurality wiring level, Para [ 0311-0333]) are on a same integrated chip (element 701).
Regarding claim 11. KUROKAWA discloses the semiconductor structure of claim 1, KUROKAWA further discloses wherein a height of the wires of the third interconnect wiring level (Fig 17, annotated middle arrow, Para [ 0311-0333]) a is greater than a height of the wires of the first interconnect wiring level (annotated lower arrow, Para [0311-0333]) and a height of the wires of the second interconnect wiring level (Fig 17, annotated upper arrow, Para [ 0311-0333]).
Regarding claim 18. KUROKAWA discloses a semiconductor structure (Fig 17, Para [0311-0333]) comprising:
a first device layer (700 [1] includes memory cell MC, Para [ 0321]);
a second device layer (700 [3] includes memory cell MC, Para [ 0321]); and
at least three interconnect wiring levels (annotated wiring structure) respectively stacked between the first device layer (700 [1] includes memory cell MC, Para [0321]) and the second device layer (700 [3] includes memory cell MC, Para [0321]);
wherein wires of an uppermost interconnect wiring level (Fig 17, annotated upper arrow, Para [ 0311-0333]) of the at least three interconnect wiring levels (annotated wiring structure) and wires of a lowermost interconnect wiring level (annotated lower arrow, Para [0311-0333]) of the at least three interconnect wiring levels (annotated wiring structure) have a minimum pitch which is smaller than a minimum pitch of wires (Fig 17, annotated upper/lower arrow, Para [ 0311-0333]) of at least one remaining interconnect wiring level (Fig 17, annotated middle arrow, Para [ 0311-0333]) of the at least three interconnect wiring levels; and
wherein the at least one remaining interconnect wiring level (Fig 17, annotated middle arrow, Para [ 0311-0333]) is stacked between the uppermost interconnect wiring level (Fig 17, annotated upper arrow, Para [ 0311-0333]) and the lowermost interconnect wiring level (annotated lower arrow, Para [0311-0333]).
Regarding claim 19. KUROKAWA discloses the semiconductor structure of claim 18, KUROKAWA further discloses further comprising:
a backside back-end-of-line metallization structure (element layer 701, Para [ 0310-0315]) under the first device layer (700 [1] includes memory cell MC, Para [0321]); and a frontside back-end-of-line metallization (annotated front side structure) structure over the second device layer (700 [3] includes memory cell MC, Para [0321]).
Regarding claim 20. KUROKAWA discloses the semiconductor structure of claim 18, KUROKAWA further discloses further comprising a via ( annotated via right side) connecting the uppermost interconnect wiring level (Fig 17, annotated upper arrow, Para [ 0311-0333]) to at least one other remaining interconnect wiring level (Fig 17, annotated middle arrow, Para [ 0311-0333]) of the at least three interconnect wiring levels (annotated wiring structure), wherein the at least one other remaining interconnect wiring level (Fig 17, annotated middle arrow, Para [ 0311-0333]) is stacked over the lowermost interconnect wiring level (Fig 17, annotated lower arrow, Para [ 0311-0333]) and wires of the at least one other remaining interconnect wiring level have a minimum pitch (Fig 17, annotated middle arrow, Para [ 0311-0333]) which is the same as the minimum pitch of the wires of the lowermost interconnect wiring level (Fig 17, annotated lower arrow, Para [ 0311-0333]).
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-17 are rejected under 35 U.S.C. 103 as being unpatentable over KUROKAWA et al (US 2026/0255633 A1; hereafter KUROKAWA) in view of TAI et al (US 2017/0005094 A1; hereafter TAI).
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Regarding claim 12. KUROKAWA discloses a semiconductor structure (Fig 17, Para [0311-0333]) comprising:
a first device layer (700 [1] includes memory cell MC, Para [ 0321]) comprising one or more transistors (700 [1] includes memory cell MC, Para [ 0321]);
a second device layer (700 [3] includes memory cell MC, Para [ 0321]) stacked over the first device layer and comprising one or more transistors (700 [3] includes memory cell MC, Para [0321]); and
a plurality of interconnect wiring levels (Fig 17, annotated plurality wiring level with arrows, Para [0311-0333]) stacked between the first device layer and the second device layer,
wherein the plurality of interconnect wiring levels (Fig 17, annotated plurality wiring level with arrows, Para [0311-0333]) comprise:
a first interconnect wiring level (Fig 17, annotated lower arrow, Para [ 0311-0333]) stacked over the first device layer (700 [1] includes memory cell MC, Para [ 0321]), wherein wires of the first interconnect wiring level (Fig 17, annotated lower arrow, Para [ 0311-0333]) are spaced apart from each other at a first pitch (Fig 17, annotated lower arrow, Para [ 0311-0333]);
a second interconnect wiring level (Fig 17, annotated upper arrow, Para [ 0311-0333]) stacked over the first interconnected wiring level (Fig 17, annotated lower arrow, Para [ 0311-0333]) and under the second device layer (700 [3] includes memory cell MC, Para [ 0321]), wherein wires of the second interconnect wiring level are spaced apart from each other at a second pitch (Fig 17, annotated upper arrow, Para [ 0311-0333]); and
at least a third interconnect wiring level (Fig 17, annotated middle arrow, Para [ 0311-0333]) stacked between the first interconnect wiring level (annotated lower arrow, Para [0311-0333]) and the second interconnect wiring level (Fig 17, annotated upper arrow, Para [ 0311-0333]), wherein wires of the third interconnect wiring level (Fig 17, annotated middle arrow, Para [ 0311-0333]) are spaced apart from each other at a third pitch (Fig 17, annotated middle arrow, Para [ 0311-0333]), and the third pitch (Fig 17, annotated middle arrow, Para [ 0311-0333]) is greater than the first pitch (Fig 17, annotated lower arrow, Para [ 0311-0333]) and the second pitch (Fig 17, annotated upper arrow, Para [ 0311-0333]).
But KUROKAWA does not disclose explicitly a first device layer corresponding to a first doping type; a second device layer to a second doping type.
In a similar field of endeavor, TAI discloses a first device layer corresponding to a first doping type (Fig 16, Para [0072-0076]); a second device layer to a second doping type (Fig 16, Para [0072-0076]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine KUROKAWA in light of TAI teaching “a first device layer corresponding to a first doping type (Fig 16, Para [0072-0076]); a second device layer to a second doping type (Fig 16, Para [0072-0076])” for further advantage such as to enhance carrier mobility and improve device performance.
Regarding claim 13. KUROKAWA and TAI discloses the semiconductor structure of claim 12, KUROKAWA further discloses further comprising:
a backside back-end-of-line metallization structure (element layer 701, Para [ 0310-0315]) under the first device layer (700 [1] includes memory cell MC, Para [0321]); and a frontside back-end-of-line metallization structure (annotated front side structure) over the second device layer (700 [3] includes memory cell MC, Para [0321]).
Regarding claim 14. KUROKAWA and TAI disclose the semiconductor structure of claim 13, KUROKAWA further discloses further comprising a via (annotated via right side) connecting the second device layer (700 [3] includes memory cell MC, Para [0321]) to the third interconnect wiring level (Fig 17, annotated middle arrow, Para [0311-0333])
Regarding claim 15. KUROKAWA and TAI disclose the semiconductor structure of claim 13, KUROKAWA further discloses further comprising a via (annotated via right side) connecting the second device layer (700 [3] includes memory cell MC, Para [0321]) to the second interconnect wiring level (Fig 17, annotated upper arrow, Para [0311-0333]).
Regarding claim 16. KUROKAWA and TAI disclose the semiconductor structure of claim 13, KUROKAWA further discloses further comprising a via (annotated via right side) connecting the second interconnect wiring level (Fig 17, annotated upper arrow, Para [0311-0333]) to the first interconnect wiring level (annotated lower arrow, Para [0311-0333]).
Regarding claim 17. KUROKAWA and TAI disclose the semiconductor structure of claim 13, KUROKAWA further discloses wherein the plurality of interconnect wiring levels (Fig 17, annotated plurality wiring level with arrows, Para [0311-0333]) further comprise a fourth interconnect wiring level ( annotated fourth wiring level) stacked over the third interconnect wiring level (Fig 17, annotated middle arrow, Para [ 0311-0333]) and between the first interconnect wiring level (annotated lower arrow, Para [0311-0333]) and the second interconnect wiring level (Fig 17, annotated upper arrow, Para [ 0311-0333]), wherein wires of the fourth interconnect wiring level ( annotated fourth wiring level) are spaced apart from each other at a fourth pitch ( annotated fourth wiring level), and the fourth pitch is greater than the first pitch (annotated lower arrow, Para [0311-0333]) and the second pitch (Fig 17, annotated upper arrow, Para [ 0311-0333]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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