Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 3/9/2026 have been fully considered but they are not persuasive. Applicant alleges that: “Yap does not teach or suggest “… shifting the one or more first configurable memory bits with the one or more second configuration bits by an amount in accordance with the second scan chain value… .” Firstly, as will be further discussed by the 112B rejection, the concept of shifting configuration bits by an amount in accordance with the second scan chain value is unclear and does not appear to be supported in the specification. The disclosure does support the concept of “shifting the configuration bits by an amount equal to the scan chain” as in para. 95 or “shift the one or more bitstreams a length of the scan chain,” as in para. 10 and therefore, this limitation is interpreted in this action in accordance with what is described in the specification.
Yap does indeed teach “shifting the one or more first configurable memory bits with the one or more second configuration bits by [an amount equal to the scan chain length].” Each of the registers in fig. 3A (R1 310-1, R2 310-2, R3 310-3, R4 310-4) are considered to be equivalent to the configuration flip-flops required in claim 1, as it is well known in the art that a 1 bit-register is effectively a single flip-flop. Further, any information stored in these registers is considered to be configurable memory bits because they configure the functioning of the logic block 340, as they are input to the logic block. After the scan capture phase, information stored in these registers is shifted out as second configuration bits are shifted in, by the length of the scan chain. For example, see fig. 3B, the first configuration bit of the second set of configuration bits is shifted into register R1 as the value in register R4 is shifted out. This continues until all four configuration bits of the first set have been shifted in (5-8, in periods P5-P9), and all previous bits in the config flip flops are shifted out (see Scan-out = V, for p5-p8).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2, 4-7, 9-10, 12-14, 16-17, 19-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, recites “providing… one or more second configuration bits to the one or more configuration flip-flops by shifting the one or more first configuration bits with the one or more second configuration bits by an amount in accordance with the second scan chain value.” It is unclear what the relationship is between the second scan chain value and the amount shifted is, especially considering the examiner would expect an individual scan chain value to be binary. Further, upon consultation of the specification, this limitation does not seem to have support. The disclosure does support the concept of “shifting the configuration bits by an amount equal to the scan chain” as in para. 95 or “shift the one or more bitstreams a length of the scan chain,” as in para. 10. Therefore, this limitation is interpreted in this action in accordance with what is described in the specification (i.e., para. 95). If this is the correct interpretation, appropriate correction is required. Otherwise, Examiner requests that the location of support for this limitation in the specification be provided and further clarification on the intended relationship between the scan chain value and the amount shifted be explained.
Claim 4 recites a similar unclear limitation: “shifting the set of one or more bitstreams a length of the second scan chain value.” Again, it is unclear how a length of the second scan chain value and the amount to shift the set of bitstreams are related. Examiner assumes that the scan chain value has a length equal to the scan chain, but that is not clear. Further, upon consultation of the specification, this limitation does not seem to have support. The disclosure does support the concept of “shifting the configuration bits by an amount equal to the scan chain” as in para. 95 or “shift the one or more bitstreams a length of the scan chain,” as in para. 10. Therefore, this limitation is interpreted in this action in accordance with what is described in the specification (i.e., para. 95). If this is the correct interpretation, appropriate correction is required. Otherwise, Examiner requests that the location of support for this limitation in the specification be provided and further clarification on the intended relationship between the scan chain value and the amount shifted be explained.
Claims 9 and 16 correspond to claim 1, and are similarly rejected.
Claims 12 and 21 correspond to claim 4, and are similarly rejected.
At least by their dependency on one of claims 1, 9, or 16, Claims 2, 5-7, 10, 13-14, 17, 19-20, 22-23 are similarly rejected under 112B.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-2, 4-7, 9-10, 12-14, 16-17, and 19-23 are rejected under 35 U.S.C. 103 as being unpatentable over Yap (US Publication No. 20230317192) in view of Souef (US Patent No. 6671870) and Vrudhula (US Publication No. 20220263508).
Regarding claim 1, Yap discloses:
A method for testing reconfigurable hardware designs,
the method comprising: … generating, by the one or more processors and using an automatic test pattern generation (ATPG) system, a set of one or more test patterns and a set of one or more bitstreams, wherein (i) the set of one or more test patterns comprise a set of one or more scan chain values and a set of one or more input values and (ii) a functionality of the reconfigurable hardware design is configured in accordance with the set of one or more bitstreams; (para. 36, scan test vectors may be generated by ATPG tools.) A scan test vector is both a test pattern and a bitstream, as it is a pattern to be used in a test and a sequence of bits. (see para. 46: As shown in FIG. 3B, in waveform 348, Scan_en 346 is asserted from P1 to a time in P4 so circuit 300 is in shift mode and input signal Scan_in 356 propagates through the scan chain (e.g. from Scan_in 356 via mux 315-1 to R1 310-1 (and via mux 315-2) to R2 310-2 (and via mux 315-3) to R3 310-3 and (via mux 315-4) to R4 310-4) during the time when Scan_en 346 is asserted. Accordingly, in waveform 358, Scan_in 356 is shown with serial input data (indicated by labels 1, 2, 3, 4 during the time when Scan_en 346 is asserted. And see para. 49: Further, at time P4, scan has propagated via the scan chain to all inputs (e.g. A 320-1 (from R1 310-1), B 320-2 (from R2 310-2), C 320-3 (from R3 310-3), and D 320-4 (from R4 310-4)) of logic block 340 so that E:F 364 is valid as shown by waveform 366. Signals E:F 364 indicate when inputs to logic block 340 are valid so that logic block 340 can then be exercised (e.g. in a subsequent scan capture mode). The serial scan test vector (a bitstream) is provided as input to the logic block of the PLD (reconfigurable hardware design), thus configuring its functionality. (also see para. 42: input signals In[0] 315-1 and In[1] 315-2 may reflect a primary input or the output of some other blocks and these paths may form part of the scan test.)
providing, by the one or more processors, in accordance with an ATPG test method and using a test architecture, a first test pattern of the set of one or more test patterns and a first bitstream of the set of one or more bitstreams to the reconfigurable hardware design by providing (i) a first scan chain value of the set of one or more scan chain values to the scan chain, (see para. 46 with fig. 3A and 3B: As shown in FIG. 3B, in waveform 348, Scan_en 346 is asserted from P1 to a time in P4 so circuit 300 is in shift mode and input signal Scan_in 356 propagates through the scan chain (e.g. from Scan_in 356 via mux 315-1 to R1 310-1 (and via mux 315-2) to R2 310-2 (and via mux 315-3) to R3 310-3 and (via mux 315-4) to R4 310-4) during the time when Scan_en 346 is asserted. Accordingly, in waveform 358, Scan_in 356 is shown with serial input data (indicated by labels 1, 2, 3, 4 during the time when Scan_en 346 is asserted.)
(ii) a first input value of the set of one or more input values to a primary input of the reconfigurable hardware design, (see para. 52: input signals In[0] 315-1 and In[1] 315-2 may reflect a primary input or the output of some other blocks (e.g. coupled to In[0] 315-1 and In[1] 315-2) and these paths may form part of the scan test. Thus, during the scan capture cycle, when Scan_en 346 is de-asserted (e.g. as shown in waveform 348 in FIG. 3B, at a time in P4) and Clk 352 is active, data on [E:F] 364 can change because In[0] 368 and In[1] 372 are being captured through registers R1 310-1 and R2 310-2, so that inputs to logic block 340 could change.)
and (iii) one or more first configuration bits to one or more configuration flip-flops of the reconfigurable hardware design, (see para. 46 with fig. 3A and 3B: As shown in FIG. 3B, in waveform 348, Scan_en 346 is asserted from P1 to a time in P4 so circuit 300 is in shift mode and input signal Scan_in 356 propagates through the scan chain (e.g. from Scan_in 356 via mux 315-1 to R1 310-1 (and via mux 315-2) to R2 310-2 (and via mux 315-3) to R3 310-3 and (via mux 315-4) to R4 310-4) during the time when Scan_en 346 is asserted. Accordingly, in waveform 358, Scan_in 356 is shown with serial input data (indicated by labels 1, 2, 3, 4 during the time when Scan_en 346 is asserted. Also see para. 50: Accordingly, during the scan capture phase, logic block operates on the input data (at logic block inputs A 320-1, B 320-2, C 320-3, and D 320-4) at the rising edge of Clk signal 352 (shown by the vertical heavy grey line).) It is well understood that registers are comprised of flip-flops, therefore input A 320-1, B 320-2, C 320-3, and D 320-4 are flip-flops in this embodiment. They are additionally considered to be configuration flip-flops of the reconfigurable hardware design as they are inputs to logic block 340, thus configuring its performance.
wherein the test architecture comprises a configuration controller that is configured to encode the first bitstream of the set of one or more bitstreams into the one or more first configuration bits in accordance with a format that corresponds to an architecture of the reconfigurable hardware design; (para. 35: ATE may input scan test data serially and the scan test data may be generated by Automatic Test Pattern Generator (ATPG) tools.) The scan test data is considered to be one or more bitstreams, as the data is a series of bits. The ATE is effectively a configuration controller because it encodes the bitstreams by serially inputting them (a format corresponding to the reconfigurable hardware design).
providing, by the one or more processors, in accordance with the ATPG test method and using the test architecture, a second test pattern of the set of one or more test patterns and a portion of a second bitstream of the set of one or more bitstreams to the reconfigurable hardware design by providing (i) a second scan chain value of the set of one or more scan chain values to the scan chain, (see fig. 5B: scan_in during P5-P9 is [5,6,7,8], considered to be a second scan chain value provided to the scan chain. Also see para. 57: Further, from P5 through P8 (during the time when Scan_en 346 is asserted), new scan input data (indicated by labels 5, 6, 7, and 8, in waveform 356 for Scan_in 358) propagates through the scan chain.) (ii) a second input value of the set of one or more input values to the primary input of the reconfigurable hardware design, (see fig 5B: In[0] and In[1]: during p6-p10 In[0] is In[0]_2 and In[1] is In[1]_2, different from the first input values in[0]_1 and in[1]_1 provided to a primary input of the reconfigurable hardware design. See para. 60: As outlined above, when Scan_en 346 is de-asserted, a clock (e.g. rising edge of Clk 352, which initiates P10) is used to capture the data: (a) at nodes E and F into registers R3 310-3 and R4 310-4, respectively, and (b) from In[0] and In[1] into registers R1 310-1 and R2 310-2. respectively. Thus, in P10, subsequent to the rising edge of Clk 352, during the capture cycle, when Scan_en 346 is de-asserted and Clk 352 is active, logic block output [E:F] 364 may change because inputs (In[0] 368 and In[1] 372 captured through registers R1 310-1 and R2 310-2) to logic block 340 could change but these are invalid data (in P10, subsequent to the rising edge of Clk 352).)
and (iii) one or more second configuration bits to the one or more configuration flip-flops by shifting the one or more first configuration bits with the one or more second configuration bits by an amount in accordance with the second scan chain value, wherein the configuration controller is configured to encode the portion of the second bitstream into the one or more second configuration bits; (see fig. 5B: scan_in during P5-P9 is [5,6,7,8], considered to be a second scan chain value provided to the scan chain. Also see para. 55: At a time in P5, Scan_en 346 is re-asserted and circuit 300 reverts to shift mode from the prior scan capture mode as shown in waveform 348. In shift mode, the scan chain is enabled and, in waveform 358, Scan_in 356 is shown (waveform 358) with input data (indicated by labels 5, 6, 7, 8) from a time in P5 (subsequent to assertion of Scan_en 346) to a time in P9 (when Scan_en 346 is next de-asserted). Also see para. 56: Scan_out 360 has valid data from P5 through P8, as shown in waveform 362 as data from the scan capture phase appears serially at Scan_out 360 as shown in waveform 362.) It is clear that the information stored in the configuration flip-flops (registers R1-R4) from the first round of scan testing (first configuration bits) is shifted out as the new data (second configuration bits) is scanned in. (Also see para. 35: ATE may input scan test data serially and the scan test data may be generated by Automatic Test Pattern Generator (ATPG) tools.) The scan test data is considered to be one or more bitstreams, as the data is a series of bits. The ATE is effectively a configuration controller because it encodes the bitstreams by serially inputting them (a format corresponding to the reconfigurable hardware design) as configuration bits. Also, Examiner notes that a “portion” of a bitstream could include the whole bitstream. As outlined in the 112B rejection of this claim, the limitation “shifting… by an amount in accordance with the second scan chain value” is unclear and appears to lack support in the specification. In this action it is interpreted to mean “shifting the set of one or more bitstreams a length of the scan chain.”
receiving, by the one or more processors and from the reconfigurable hardware design, (i) a first primary output value that corresponds to the first input value, (ii) a second primary output value that corresponds to the second input value, (iii) a first scan chain content that corresponds to the one or more first configuration bits, (iv) a second scan chain content that corresponds to the one or more second configuration bits; (para. 52: During the period when Scan_en 346 is de-asserted, a clock (e.g. rising edge of Clk 352, which initiates P5) is used to capture the data: (a) at nodes E and F into registers R3 310-3 and R4 310-4, respectively (in FIG. 3A), and (b) from In[0] and In[1] into registers R1 310-1 and R2 310-2. respectively (in FIG. 3A) and see para. 60: As outlined above, when Scan_en 346 is de-asserted, a clock (e.g. rising edge of Clk 352, which initiates P10) is used to capture the data: (a) at nodes E and F into registers R3 310-3 and R4 310-4, respectively, and (b) from In[0] and In[1] into registers R1 310-1 and R2 310-2. respectively. Also see para. 43: Next, Scan_en 346 may be asserted so that circuit 300 reverts to shift mode and primary input In[0] 315-1 and In[1] 315-2 and output [E:F] 364 are captured in 310-1, 310-2, 310-3, 310-4, which are scanned out serially via Scan_out 360. Scan_out data 360 may be captured and compared to expected values using ATE (not shown in FIG. 3A) to detect errors. ) Scanned out In[0]_1 and In[1]_1 are first primary outputs corresponding to the first input values (In[0]_1 and In[1]_1) during the first scan test cycle. Scanned out In[0]_2 and In[1]_2 are second primary outputs corresponding to the second input values (In[0]_2 and In[1]_2) during the second scan test cycle. Scanned out [E:F] 364 is considered to be first scan chain content corresponding to the first configuration bits in the first scan cycle, because [E:F] is the result of applying the logic block 340 to the first configuration bits (scan_in [1,2,3,4]). Scanned out [E:F] 364 is considered to be second scan chain content corresponding to the second configuration bits in the second scan cycle, because it is the result of applying the logic block 340 to the second configuration bits (scan_in [5,6,7,8]).
And determining, by the one or more processors, one or more faults associated with the reconfigurable hardware design based on a comparison of the first primary output value, the second primary output value, the first scan chain content, and the second scan chain content with one or more respective expected outcomes corresponding to the functionality of the reconfigurable hardware design. (para. 43: Next, Scan_en 346 may be asserted so that circuit 300 reverts to shift mode and primary input In[0] 315-1 and In[1] 315-2 and output [E:F] 364 are captured in 310-1, 310-2, 310-3, 310-4, which are scanned out serially via Scan_out 360. Scan_out data 360 may be captured and compared to expected values using ATE (not shown in FIG. 3A) to detect errors.) Scan_out data is captured and compared to expected values to detect errors each scan cycle. As can be seen in fig. 3B, multiple scan cycles are performed.
However, Yap does not explicitly disclose:
inserting, by one or more processors, a scan chain into a reconfigurable hardware design that is associated with an integrated circuit comprising a redacted design.
In the analogous art of automatic test generation systems, Souef teaches:
inserting, by one or more processors, a scan chain into a reconfigurable hardware design that is associated with an integrated circuit. (col. 8, lines 42-43, insert scan chains in an integrates circuit under design.)
It would have been obvious, to one of ordinary skill in the art, having the teachings of Yap and Souef before the effective filing date of the claimed invention, to incorporate the scan chain insertion taught by Souef into the method of scan testing disclosed by Yap, to allow for benefits such as reduced area cost when implementing test insertion, irrespective of the topology of the circuit (Souef, col. 2, lines 28-33).
However, the combination of Yap and Souef does not explicitly teach:
An integrated circuit comprising a redacted design.
In the analogous art of automatic test generation for integrated circuits, Vrudhula teaches:
An integrated circuit comprising a redacted design. (para. 104, New automatic test pattern generation (ATPG) algorithms can be used in an ATPG tool for… ICs. … The final set… in the IC design is S.sub*… which results in a Boolean function f.sub* are secrets which should be withheld from the adversary. It is assumed that a vendor that tests the IC is an adversary. In that case, one may wish to provide the vendor with an alternate set of STVVs, which allow the circuit to be tested without revealing S.sub* and f.sub* [secret values integral to the design of the circuit].)
It would have been obvious, to one of ordinary skill in the art, having the teachings of Yap, Souef, and Vrudhula before the effective filing date of the claimed invention, to incorporate protecting the secret design of an IC during testing into the method of scan testing disclosed by the combination , to allow for benefits such as allowing the circuit to be tested without revealing its design (Vrudhula, para. 104).
Regarding claim 2, the combination of Yap, Souef, and Vrudhula teaches the method of claim 1. Yap further teaches:
Wherein (i) the ATPG test method comprises a base ATPG test method, and (ii) the one or more configuration flip-flops comprise one or more additional primary inputs. (para. 38, Values in registers R1 310-1 and R2-310-2 may appear as inputs A 320-1 and B 320-2 to logic block 340. [It is well understood that registers are comprised of flip-flops, therefore input A 320-1 and B 320-2 are flip-flops in this embodiment. They are additionally considered to be configuration flip-flops as they are inputs to logic block 340, thus configuring its performance.] And para 41, to test logic block 340, with Scan_en 346 asserted, data may be serially input via Scan_in 356 and when inputs A 320-1, B 320-2, C 320-3, and D 320-4 correctly reflect a desired input, the scan test vector has been scanned in and scan in phase is complete.) The configuration flip-flops is the set of all registers R1-R4 of fig. 3A. During the capture phase, input values In[0] and In[1] are input to logic block 34 via registers R1 and R2. The configuration bits in R3 and R4 are effectively “additional primary inputs”.
Regarding claim 4, the combination of Yap, Souef, and Vrudhula teaches the method of claim 1. Yap further teaches:
Shifting the set of one or more bitstreams a length of the second scan chain value. (para. 36, Scan testing may be viewed as involving three phases: (i) a scan in phase, to input the test vector, (ii) a scan capture phase (e.g. when the device is placed into non-test or operating mode) and the test vector input (in the scan in phase) exercises the functional blocks and output is captured, and (iii) a scan out phase (e.g. when the device may be placed in shift mode again) and output data is shifted out.) Test vectors are considered to be bitstreams as they are a sequence of bits. Each test involves inputting a test vector and shifting it the length of the scan chain until it is output. As outlined in the 112B rejection of this claim, this limitation in unclear and appears to lack support in the specification. In this action it is interpreted to mean “shifting the set of one or more bitstreams a length of the scan chain.”
Regarding claim 5, the combination of Yap, Souef, and Vrudhula teaches the method of claim 1. Yap further teaches:
Wherein the ATPG test method comprises an overlapped ATPG test method, and the method further comprising: loading the scan chain and set of one or more bitstreams simultaneously. (para. 40, (d) at each clock cycle, data [a test vector] is shifted from: input Scan_In 356 to R1 310-1; output of R1 310-1 to R2 310-2; output of R2 310-2 to R3 310-3; output of R3 310-3 to R4 310-4; output of R4 310-4 to Scan_out 360. The path outlined in (d) above represents a scan chain.) The set of test vectors are considered to be the set of bitstreams as each test vector is a sequence of bits. The test vector is loaded into/along the scan chain; therefore, both are loaded simultaneously.
Regarding claim 6, the combination of Yap, Souef, and Vrudhula teaches the method of claim 1. Yap further teaches:
Wherein the ATPG test method comprises an overlapped parallel ATPG test method, and the method comprises: loading a plurality of bits per cycle; and overlapping loading the set of one or more bitstreams with loading of the scan chain. (para. 40, (d) at each clock cycle, data [a test vector] is shifted from: input Scan_In 356 to R1 310-1; output of R1 310-1 to R2 310-2; output of R2 310-2 to R3 310-3; output of R3 310-3 to R4 310-4; output of R4 310-4 to Scan_out 360. The path outlined in (d) above represents a scan chain.) The set of test vectors are considered to be the set of bitstreams as each test vector is a sequence of bits. The test vector is loaded into/along the scan chain each clock cycle; therefore, the loading of both is overlapped.
Regarding claim 7, the combination of Yap, Souef, and Vrudhula teaches the method of claim 1. Yap further teaches:
wherein the reconfigurable hardware design comprises a field- programmable gate array (FPGA), or an embedded FPGA (e-FPGA) used in an application-specific integrated circuit (ASIC). (FPGA 102 may be a standalone FPGA 102A and/or take the form of an embedded FPGA (eFPGA) 102B. eFPGAs 102B may be viewed as fully integrated programmable logic Intellectual Property (IP) cores that form part of an ASIC.)
Claims 9-10, 12-14, 16-17, 19-20, 21, 22, and 23 correspond to claims 1-2, 4-6, 1-2, 5-6, 4, 7, and 7 (respectively), and are rejected accordingly.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK K BARNETT whose telephone number is (571)270-0431. The examiner can normally be reached M-Th 8-5, F 8-4 EST.
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/JACK KENSINGTON BARNETT/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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