DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Anderson et al. (U.S. Publication No. 2007/0108528 A1; hereinafter Anderson).
With respect to claim 11, Anderson discloses a semiconductor structure comprising: a plurality of fins [1161,1162,1163] formed over a substrate, the plurality of fins comprising a first fin comprising a first height, a second fin comprising a second height different than the first height, and a third fin comprising a third height different than the first height and the second height; and a gate [1551,1552,1553] formed over the first fin, the second fin, and the third fin; wherein an effective width of the first fin is less than an effective width of the second fin and the effective width of the second fin is less than an effective width of the third fin (See ¶[0005-0008]; The effective fin width is determined by the fin height (e.g., short wide fins can cause partial depletion of a channel)).
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With respect to claim 12. The semiconductor structure of claim 11, wherein topmost surfaces of each fin of the plurality of fins are coplanar (See Figure 15).
Allowable Subject Matter
Claims 1-10, 16-25 are allowed.
Claims 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claims 1-5, none of the prior art teaches or suggests, alone or in combination, a semiconductor structure comprising: a first shallow trench isolation (STI) region formed over a first portion of a substrate; a second STI region formed over a second portion of the substrate, a first fin formed in and above the first STI region; a second fin formed in and above the second STI region, and a bottom dielectric isolation (BDI) region positioned directly between the first fin and the substrate, thereby providing the first fin having a first effective width and the second fin having a second effective width different than the first effective width.
With respect to claims 6-10, none of the prior art teaches or suggests, alone or in combination, a semiconductor structure comprising: a first bottom dielectric isolation (BDI) region positioned directly between the first fin and the n-type region of the substrate; and a second BDI region positioned directly between the second fin and the p-type region of the substrate, wherein a height of the second BDI region is different than a height of the first BDI region, thereby providing the first fin having a first effective width and the second fin having a second effective width different than the first effective width.
With respect to claims 13-15, none of the prior art teaches or suggests, alone or in combination, a first bottom dielectric isolation (BDI) region positioned directly between the first fin and the substrate; a second BDI region positioned directly between the second fin and the substrate; and a third BDI region positioned directly between the third fin and the substrate.
With respect to claims 16-20, none of the prior art teaches or suggests, alone or in combination, a method for forming a semiconductor device, the method comprising: forming a first shallow trench isolation (STI) region over a first portion of a substrate; forming a second STI region over a second portion of the substrate, forming a first fin in and above the first STI region; forming a second fin in and above the second STI region, and forming a bottom dielectric isolation (BDI) region directly between the first fin and the substrate, thereby providing the first fin having a first effective width and the second fin having a second effective width different than the first effective width.
With respect to claims 21-25, none of the prior art teaches or suggests, alone or in combination, a method for forming a semiconductor device, the method comprising: forming a first bottom dielectric isolation (BDI) region directly between the first fin and the n-type region of the substrate; and forming a second BDI region directly between the second fin and the p-type region of the substrate, wherein a height of the second BDI region is different than a height of the first BDI region, thereby providing the first fin having a first effective width and the second fin having a second effective width different than the first effective width.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Frougier et al. (U.S. Publication No. 2022/0231020 A1) discloses fins with multiple effective widths but fails to disclose a first bottom dielectric isolation (BDI) region positioned directly between the first fin and the n-type region of the substrate; and a second BDI region positioned directly between the second fin and the p-type region of the substrate, wherein a height of the second BDI region is different than a height of the first BDI region, thereby providing the first fin having a first effective width and the second fin having a second effective width different than the first effective width.
-Xiong et al. (U.S. Patent No. 7,638,843 B2) discloses multi-gate device with fins of multiple effective widths but fails to disclose a first shallow trench isolation (STI) region formed over a first portion of a substrate; a second STI region formed over a second portion of the substrate, a first fin formed in and above the first STI region; a second fin formed in and above the second STI region, and a bottom dielectric isolation (BDI) region positioned directly between the first fin and the substrate, thereby providing the first fin having a first effective width and the second fin having a second effective width different than the first effective width.
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/JONATHAN HAN/Primary Examiner, Art Unit 2818