DETAILED ACTION
This action is responsive to the application filed on 12/12/2023. Claims 1-20 are pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-4 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regards to claim 3, lines 2-3 the limitations “…storing a third set of state values associated with a third subset of threads of the first wave into a second bin based on each of the second subset of threads including a second set of instructions to be executed” lacks clarity. The limitation lacks clarity because it appears to be inconsistent with the specification. For example, paragraphs [0021 and 0029] disclose storing state values associated with subsets of threads into bins based on the subsets of threads (e.g. same subset of threads) including a set of instructions to be executed. However, the specification does not disclose storing state values associated with a subset of threads into a bin based on a second (e.g. different) subset of threads including a second set of instructions, thus the limitations stating storing state values associated with a third subset of threads into a second bin based on a second subset of threads lacks clarity because it is inconsistent with the specification.
The examiner believes the claim should state “…storing a third set of state values associated with a third subset of threads of the first wave into a second bin based on each of the third subset of threads including a second set of instructions to be executed”, and for purposes of examination will interpret the limitation as such. (See MPEP 2173.03, “A claim, although clear on its face, may also be indefinite when a conflict or inconsistency between the claimed subject matter and the specification disclosure renders the scope of the claim uncertain as inconsistency with the specification disclosure or prior art teachings may make an otherwise definite claim take on an unreasonable degree of uncertainty.)
Claim 4 is dependent upon claim 3 above and therefore is similarly rejected for including the deficiencies of claim 3 above.
In regards to claim 15, lines 2-3 the limitation stating “…the stored state values” lacks clarity. The limitation lacks clarity because it is unclear if the stored state values are referring to “the first set of state values” stored in the first sort bin of claim 14, line 1 or “the third set of state values” stored in the first sort bin of claim 14, line 2?
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by NPL reference “Intel Arc Graphics Developer Guide for Real-time Ray Tracing in Games” (cited on IDS filed on 4/17/2024) hereby referred to as Intel.
In regards to claim 1, Intel discloses A method comprising: forming a third wave of threads (pages 3 and 5: wherein a thread sorting unit of Fig. 2 forms a third wave of XVE threads, shown as including stack ID’s 0,2,4,6,8,9,10 and 13 (note: XVEs are Single Instruction, Multiple Data (SIMD) compute units which execute ray-tracing shaders in groups of 8 or 16 shader threads. Thus, XVE would execute 8 threads including the above stack ID’s)) from: a first subset of threads of a first wave based on each of the first subset of threads including a first set of instructions to be executed corresponding to a first sort key (page 5: wherein a thread sorting unit of Fig. 2 forms a third wave of XVE threads from a first subset of threads (threads corresponding to stack ID’s 0,2,4,6) from a first wave (wave including stack ID’s 0-7) based on each of the first subset of threads including instructions to a same shader to be executed corresponding to a first shader record address (first sort key)) and a second subset of threads of a second wave based on each of the second subset of threads including the first set of instructions to be executed corresponding to the first sort key (page 5: wherein a thread sorting unit of Fig. 2 forms a third wave of XVE threads from a second subset of threads (threads corresponding to stack ID’s 8,9,10,13) from a second wave (wave including stack ID’s 8-15) based on each of the second subset of threads including instructions to a same shader to be executed corresponding to the first shader record address (first sort key)) and emitting the third wave for execution. (page 5: “The TSU is a dedicated hardware block which is able to sort and re-emit shader threads to maximize SIMD coherence from divergent workloads”. Thus, the third wave is emitted)
In regards to claim 2, Intel discloses The method of claim 1 (see rejection of claim 1 above) further comprising: storing a first set of state values associated with the first subset of threads of the first wave into a first bin based on each of the first subset of threads including the first set of instructions to be executed (page 5: wherein a first set of stack ID’s associated with a first subset of threads (threads corresponding to stack ID’s 0,2,4,6) from a first wave (wave including stack ID’s 0-7) are stored into a bin based on each of the first threads including instructions of a shader to be executed (“The TSU will bin the stack IDs by shader record address. It can then emit coherent XVE threads as they are formed, all of which will be the same shader, and share the same shader records. During binning, the stack IDs and shader-record addresses are stored in an on-chip sorting cache” (see page 5 and Fig. 2)) and storing a second set of state values associated with the second subset of threads of the second wave into the first bin based on each of the second subset of threads including the first set of instructions to be executed. (page 5: wherein a second set of stack ID’s associated with a second subset of threads (threads corresponding to stack ID’s 8,9,10,13) from a second wave (wave including stack ID’s 8-15) are stored in a bin based on each of the second threads including instructions of the shader to be executed) (“The TSU will bin the stack IDs by shader record address. It can then emit coherent XVE threads as they are formed, all of which will be the same shader, and share the same shader records. During binning, the stack IDs and shader-record addresses are stored in an on-chip sorting cache” (see page 5 and Fig. 2))
In regards to claim 3, Intel discloses The method of claim 2 (see rejection of claim 2 above) further comprising: storing a third set of state values associated with a third subset of threads of the first wave into a second bin based on each of the second subset of threads including a second set of instructions to be executed. (page 5: wherein a third set of stack ID’s associated with a third subset of threads (threads corresponding to stack ID’s 1,3,5) from a first wave (wave including stack ID’s 0-7) are stored into a second bin based on each of the third subset of threads including instructions of a second shader to be executed (“The TSU will bin the stack IDs by shader record address. It can then emit coherent XVE threads as they are formed, all of which will be the same shader, and share the same shader records. During binning, the stack IDs and shader-record addresses are stored in an on-chip sorting cache” (see page 5 and Fig. 2))
In regards to claim 4, Intel discloses The method of claim 3 (see rejection of claim 3 above) further comprising: sorting the third subset based on a second sort key (page 5: wherein the third subset is sorted based on a second shader record address (“The TSU will bin the stack IDs by shader record address. It can then emit coherent XVE threads as they are formed, all of which will be the same shader, and share the same shader records.”) wherein the first and second sort keys are indicative of the first set of instructions to be executed and the second set of instructions to be executed, respectively. (pages 5-6: wherein the first and second shader addresses are indicative of a first set of instructions of a first shader and a second set of instructions of a second shader, respectively.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
negated by the manner in which the invention was made.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over NPL reference “Intel Arc Graphics Developer Guide for Real-time Ray Tracing in Games” (cited on IDS filed on 4/17/2024) hereby referred to as Intel and further in view of Gierach, PGPUB No. 2020/0151936.
In regards to claim 7, Intel discloses The method of claim 1 (see rejection of claim 1 above)
Intel does not explicitly disclose wherein: the first sort key is received from a user. Intel does disclose that the sort key is a shader record address, but does not explicitly indicate that the address is received from a user.
Gierach discloses wherein: the first sort key is received from a user ([0165]: wherein a shader address pointer is allocated by a user and thus received from a user).
It would have been obvious to one of ordinary skill in art before the effective filing date of the invention to modify the shader record address of Intel to be received from a user as the shader record address of Gierach. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (receiving a sort key from a user as taught in Gierach) for another (generically receiving a sort key as disclosed in Intel) to yield predictable results (receiving a sort key to repack waves of threads) (MPEP 2143, Example B).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over NPL reference “Intel Arc Graphics Developer Guide for Real-time Ray Tracing in Games” (cited on IDS filed on 4/17/2024) hereby referred to as Intel and further in view of Rogers, PGPUB No. 2014/0149710.
In regards to claim 8, Intel discloses The method of claim 1 (see rejection of claim 1 above).
Intel does not disclose wherein: the first wave is received in response to a compiler determination that the first wave has diverged by at least a threshold amount.
Rogers discloses wherein: the first wave is received in response to a compiler determination that the first wave has diverged by at least a threshold amount. ([0049 and 0055]: wherein a compiler determines whether to repack a wavefront based on determining the wavefront has diverged at least a threshold amount)
It would have been obvious to one of ordinary skill in art before the effective filing date of the invention to modify receiving of waves to be sorted and re-emitted in Intel to be based on a compiler determination of a level of divergence exceeding a threshold as taught in Rogers. It would have been obvious to one of ordinary skill in the art because sorting and repacking waves based on divergence exceeding a threshold can be used to improve performance and utilization of execution hardware (Rogers [0045, 0053 and 0055]).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over NPL reference “Intel Arc Graphics Developer Guide for Real-time Ray Tracing in Games” (cited on IDS filed on 4/17/2024) hereby referred to as Intel, Mansell, PGPUB No. 2015/0128144 and further in view of Rogers, PGPUB No. 2014/0149710.
In regards to claim 9, Intel discloses The method of claim 1 (see rejection of claim 1 above).
Intel does not disclose wherein: the first wave is received in response to a programmer-specified instruction that indicates that the first wave is expected to have diverged by at least a threshold amount.
Mansell discloses wherein: the first wave is received in response to a programmer-specified instruction that indicates that the first wave is expected to have diverged ([0032-0033 and 0067]).
It would have been obvious to one of ordinary skill in art before the effective filing date of the invention to modify receiving of waves to be sorted and re-emitted Intel to be based on a programmer-specified instruction that indicates a wave is expected to diverge as taught in Manswell. It would have been obvious to one of ordinary skill in the art because sorting and repacking waves based on programmer instruction can be useful as it allows improvement in thread execution and provides added flexibility (Rogers [0032-0033 and 0067]).
The combination of Intel and Manswell does not disclose diverged by at least a threshold amount.
Rogers discloses the first wave diverges by at least a threshold amount. ([0049 and 0055]: wherein it is determined whether to repack a wavefront based on determining the wavefront has diverged at least a threshold amount)
It would have been obvious to one of ordinary skill in art before the effective filing date of the invention to modify the divergence instruction which indicates code is expected to diverge of Manswell to indicate a level of divergence exceeding a threshold as taught in Rogers. It would have been obvious to one of ordinary skill in the art because sorting and repacking waves based on divergence exceeding a threshold can be used to improve performance and utilization of execution hardware (Rogers [0045, 0053 and 0055]). It would have been further obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (indicating divergence of at least a threshold amount as taught in Rogers) for another (indicating expected divergence as disclosed in Manswell) to yield predictable results (an instruction indicating divergence of at least a threshold amount) (MPEP 2143, Example B).
Claim(s) 10-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gierach, PGPUB No. 2020/0151936 and further in view of Sloan, PGPUB No. 2015/0221123.
In regards to claim 10, Gierach discloses A streaming wave coalescer (SWC) circuit (See Fig. 15, fixed-function circuitry (element 1510) is a streaming wave coalescer) comprising: a first sort bin configured to store a first set of state values associated with a first subset of threads, based on the first subset of threads corresponding to a first sort key ([0164 and 0174-0177]: wherein a first sort bin stores stackID/context IDs associated with a first subset of threads based on the first subset of threads corresponding to a first shader record pointer (element 1701A) (See fig. 17 for further clarity)) and a second sort bin configured to store a second set of state values associated with a second subset of threads based on the second subset of threads corresponding to a second sort key. ([0164 and 0174-0177]: wherein a second sort bin stores stackID/context IDs associated with a second subset of threads based on the second subset of threads corresponding to a second shader record pointer (element 1701B) (See fig. 17 for further clarity))
Gierach does not disclose an insert wave memory configured to receive wave data comprising a plurality of threads from a wave feed.
Sloan discloses an insert wave memory configured to receive wave data comprising a plurality of threads from a wave feed. (See Fig. 2: wherein memory (element 220) receives thread group data comprising a plurality of threads/lanes from a thread group)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the circuitry of Gierach to include an input thread memory as disclosed in Sloan. It would have been obvious because the use of additional memory in a circuit can provide low-latency data access and can reduce overall memory congestion in a processor.
In regards to claim 11, the combination of Gierach and Sloan discloses The SWC circuit of claim 10 (see rejection of claim 10 above) wherein: while the first sort bin stores the first set of state values, the first sort bin is further configured to store a third set of state values associated with a third subset of threads received at the insert wave memory based on the third subset of threads corresponding to a third sort key. ( Gierach [0164 and 0174-0177]: wherein a first sort bin stores stackID/context IDs associated with a first subset of threads (SIMD lanes/threads with context IDs/stack IDs stored in Context IDs 0-7) based on the first subset of threads corresponding to a first shader record pointer (element 1701A), the first sort bin is further configured to store a third set of stackID/context IDs corresponding to a third subset of threads (SIMD lanes/threads with context IDs/stack IDs stored in Context IDs 8-15) based on the third subset corresponding to shader record (1701A) (See fig. 17 for further clarity))
In regards to claim 12, the combination of Gierach and Sloan discloses The SWC circuit of claim 10 (see rejection of claim 10 above) further comprising: an emit wave circuit (Gierach: See Fig. 17: wherein combination of element 1507 and 1720 is interpreted to be emit wave circuitry) configured to: store an SWC wave from the first sort bin in response to an indication that the SWC wave is complete; and emit the SWC wave to shader circuitry for execution. (Gierach [0155, 0157 and 0177]: wherein when first bin is fully packed (i.e. complete), the wave is stored in element 1720 which then passes the wave to scheduler 1507 which emits the wave to shader circuitry (element 1500) (see Figs. 15 and 17 for further clarity))
In regards to claim 13, the combination of Gierach and Sloan discloses The SWC circuit of claim 12 (see rejection of claim 12 above) wherein: the first sort bin is further configured to send stored state values including the first set of state values to the emit wave circuit as the SWC wave in response to detecting that each entry of the first sort bin is full. (Gierach [0155, 0157 and 0177]: wherein the first sort bin is configured to send the context IDs/stackIDs to the emit wave circuitry in response to the sort bin being full)
In regards to claim 14, the combination of Gierach and Sloan discloses The SWC circuit of claim 13 (see rejection of claim 13 above) wherein: subsequent to the first sort bin sending the first set of state values to the emit wave circuit (Gierach [0155, 0157 and 0177]: wherein the first sort bin is configured to send the context IDs/stackIDs to the emit wave circuitry in response to the sort bin being full) the first sort bin is configured to store a third set of state values associated with a third subset of threads corresponding to a third sort key. (Gierach [0171 and 0174-0177]: wherein after a first sort bin is full the state values are emitted for shader execution; a bin would be empty or deallocated. Then subsequently a message unit may spawn a subsequent task with values being allocated to a different stack (See Fig. 16). The incoming spawn commands can store a shader record pointer to 1701A and store corresponding context ID’s/stack ID’s (third set of state values associated with a third subset of threads) to the bin. (also see [0155-0157] for details of emitting waves once bin is full))
In regards to claim 15, the combination of Gierach and Sloan discloses The SWC circuit of claim 14 (see rejection of claim 14 above) further comprising: a third sort bin configured, subsequent to the first sort bin sending the stored state values to the emit wave circuit, to store a fourth set of state values associated with a fourth subset of threads corresponding to the first sort key. (Gierach [0166, 0171 and 0174-0177]: wherein a third sort bin including shader record pointer 1701C, can store context IDs/stack IDs associated with a fourth subset of threads corresponding to the first shader record pointer. Wherein a new shader invocation can use stacks from a free stack, thus the first sort key (i.e. a first shader record pointer) can be reused by and stored in another sort bin (e.g. third sort bin), subsequent to the first sort bin sending state values to emit wave circuitry (combination of elements 1720 and 1507) and deallocating a stack which was previously used)
Allowable Subject Matter
Claims 5-6 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 17-20 are allowed.
13. The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, alone or in combination, fail to disclose or render obvious the claims filed on 12/12/2023. The prior art of record has not taught either individually or in combination and together with all other claimed features “The method of claim 2, further comprising: storing a fourth set of state values associated with a fourth subset of threads of a fourth wave into a third bin based on the fourth wave being associated with a second hard key, wherein the first wave and the second wave correspond to a first hard key” as claimed in claim 5.
The closest prior art of record, NPL reference hereby referred to as Intel and Gierach, PGPUB No. 2020/0151936 both disclose sorting of state values in different bins based on corresponding waves having a same sort key. However, neither reference discloses sorting state values of waves based on the waves corresponding to a first sort key and a first hard key, which claim 5 requires based on its dependency upon claims 1-2.
While, each reference cited below in the pertinent art section discloses sorting of waves based on execution functions or targets of diverging control flows. None of the references disclose sorting waves based upon a first sort key and a first hard key as disclosed in claim 5 above. Thus, claim 5 is allowable over the prior art.
Furthermore, the prior art of record has not taught either individually or in combination and together with all other claimed features the limitations discussed above. Thus, while some limitations may be broadly disclosed in the references above, the specific combination of limitations would not be obvious as claimed absent impermissible hindsight.
Claim 6 is dependent upon claim 5 above and therefore is similarly allowable over the prior art at least based upon dependency.
14. The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, alone or in combination, fail to disclose or render obvious the claims filed on 12/12/2023. The prior art of record has not taught either individually or in combination and together with all other claimed features “The SWC circuit of claim 10, further comprising: a junk bin configured to store a third set of state values associated with a third subset of threads received at the insert wave memory and corresponding to sort keys having a frequency value less than a frequency threshold.” as claimed in claim 16.
The closest prior art of record, NPL reference hereby referred to as Intel and Gierach, PGPUB No. 2020/0151936 both disclose sorting of state values in different bins based on corresponding waves having a same sort key. Further, each reference discloses evicting or issuing bins with partially filled threads. However, neither reference discloses including a junk bin which stores state values corresponding to sort keys a frequency value less than a frequency threshold.
Furthermore, the prior art of record has not taught either individually or in combination and together with all other claimed features the limitations discussed above. Thus, while some limitations may be broadly disclosed in the references above, the specific combination of limitations would not be obvious as claimed absent impermissible hindsight.
Thus, claim 16 is allowable over the prior art of record.
15. The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, alone or in combination, fail to disclose or render obvious the claims filed on 12/12/2023. The prior art of record has not taught either individually or in combination and together with all other claimed features “A processing system, comprising: a bus; a first processing circuit configured to issue a plurality of commands via the bus; and a second processing circuit configured to receive the plurality of commands from the first processing circuit, and comprising: dispatch circuitry comprising: an insert wave memory configured to receive wave data comprising a plurality of threads from a wave feed; and a sort memory configured to store a set of state values associated with a subset of threads received at the insert wave memory based on the subset of threads being associated with a same hard key and same sort key; and shader circuitry configured to process the plurality of threads” as claimed in claim 17.
The closest prior art of record, NPL reference hereby referred to as Intel and Gierach, PGPUB No. 2020/0151936 both disclose sorting of state values in different bins based on corresponding waves having a same sort key. However, neither reference discloses sorting state values of waves based on the waves corresponding to a same sort key and a same hard key.
While, each reference cited below in the pertinent art section discloses sorting of waves based on execution functions or targets of diverging control flows. None of the references disclose sorting waves based upon a same sort key and a same hard key as disclosed in claim 17 above. Thus, claim 17 is allowable over the prior art.
Furthermore, the prior art of record has not taught either individually or in combination and together with all other claimed features the limitations discussed above. Thus, while some limitations may be broadly disclosed in the references above, the specific combination of limitations would not be obvious as claimed absent impermissible hindsight.
Claims 18-20 are dependent upon claim 17 above and therefore are similarly allowable over the prior art at least based upon dependency.
Conclusion
16. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Oldcorn, PGPUB No. 2020/0409695 for teaching sorting and reorganizing divergent execution items based on control flow targets/functions
Saleh, PGPUB No. 2020/0004585 for teaching grouping of diverging tasks by grouping task that execute a same function into different task list in a task queue data structure
Mei, PGPUB No. 2015/0095914 for teaching sorting warps in a queue based on divergence
17. Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
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/COURTNEY P SPANN/Primary Examiner, Art Unit 2183