DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicants’ election without traverse of Species A in the reply filed on 15 May 2026 is acknowledged. Claims 11-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. The election requirement is deemed proper and made final. Applicants are reminded to indicate the withdrawn status of claims 11-16 in their next submission of a claim listing.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1, lines 10 and 11, recites “the first portion of the ones of the bit lines,” which should read “the first portions of the ones of the bit lines” for proper grammar and composition.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5-9, and 21-23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu (US20220157888A1).
Regarding claim 1, Liu teaches in Fig. 21 a three-dimensional memory device comprising:
a base insulating layer (bottommost 33) on a substrate (24) {Fig. 21, orientation of Fig. 21 may be rotated 180 degrees to achieve claimed orientation; [0048, 0052]};
a stack structure (22, 33) comprising word lines (22) and first interlayer insulating layers (33) which are alternately stacked on the base insulating layer (bottommost 33), and a second interlayer insulating layer (uppermost 33) on an uppermost one of the word lines (uppermost 22) {Fig. 21, orientation of Fig. 21 may be rotated 180 degrees to achieve claimed orientation; [0033]};
bit lines (36, 37) that are in the stack structure (22, 33) and are spaced apart from each other in a first direction (horizontal) parallel to a top surface of the substrate (24), wherein ones of the bit lines (36, 37) include respective first portions (37) that protrude from a top surface of the stack structure (22, 33) and respective second portions (36) that are in the stack structure (22, 33) {[0036]};
an outer electrode (27) on the stack structure (22, 33) and on the first portion (37) of the ones of the bit lines (36, 37) {[0035]}; and
a dielectric layer (33 between 22 and 27) between the outer electrode (27) and the first portions (37) of the ones of the bit lines (36, 37), wherein the dielectric layer (33 between 22 and 27) surrounds side surfaces of the first portions (37) of the ones of the bit lines (36, 37) in plan view {[0033]},
wherein the outer electrode (27) is spaced apart from the first portions (37) of the ones of the bit lines (36, 37) with the dielectric layer (33 between 22 and 27) interposed therebetween {Fig. 21}.
Regarding claim 2, Liu teaches the three-dimensional memory device of claim 1, and Liu further teaches further comprising:
an upper insulating layer (12) on top surfaces of the bit lines (36, 37), a top surface of the dielectric layer (33 between 22 and 27), and a top surface of the outer electrode (27) {Fig. 21, orientation of Fig. 21 may be rotated 180 degrees to achieve claimed orientation; [0029], Base substrate 12 … may comprise dielectric material}.
Regarding claim 5, Liu teaches the three-dimensional memory device of claim 1, and Liu further teaches wherein a first thickness of one of the first portions (37) of the bit lines (36, 37) in a third direction (vertical) perpendicular to the top surface of the substrate (24) is greater than a second thickness of one of the word lines (22) in the third direction (vertical) and a third thickness of one of the first interlayer insulating layers (33 between adjacent 22s) in the third direction (vertical) {Fig. 21}.
Regarding claim 6, Liu teaches the three-dimensional memory device of claim 1, and Liu further teaches wherein the stack structure (22, 33) further comprises:
storage patterns (40) spaced apart from each other in a third direction (vertical) perpendicular to the top surface of the substrate (24) {[0038]},
wherein the storage patterns (40) are between a first one of the bit lines (36, 37) and respective ones of the word lines (22) {Fig. 21}.
Regarding claim 7, Liu teaches the three-dimensional memory device of claim 6, and Liu further teaches wherein the storage patterns (40) are on a side surface of one of the bit lines (36, 37) in plan view {Fig. 21}.
Regarding claim 8, Liu teaches the three-dimensional memory device of claim 6, and Liu further teaches wherein ones of the word lines (22) are electrically connected to respective ones of the storage patterns (40) {[0043]}.
Regarding claim 9, Liu teaches the three-dimensional memory device of claim 6, and Liu further teaches wherein the storage patterns (40) include at least one of selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In) {[0039]}.
Regarding claim 21, Liu teaches in Fig. 21 a three-dimensional memory device comprising:
a base insulating layer (bottommost 33) on a substrate (24) {Fig. 21, orientation of Fig. 21 may be rotated 180 degrees to achieve claimed orientation; [0048, 0052]};
word lines (22) and interlayer insulating layers (33) which are alternately stacked on the base insulating layer (bottommost 33) {Fig. 21, orientation of Fig. 21 may be rotated 180 degrees to achieve claimed orientation; [0033]};
bit lines (36, 37, 28) that are in the word lines (22) and the interlayer insulating layers (33), and are spaced apart from each other in a first direction (horizontal) parallel to a top surface of the substrate (24), wherein the bit lines (36, 37, 28) each includes a first portion (37, 28) that protrudes from a top surface of an uppermost one of the interlayer insulating layers (33) and a second portion (36) that is in the word lines (22) and the interlayer insulating layers (33) {[0036]};
a dielectric layer (33 between 22 and 27) on side surfaces of the respective first portions (37, 28) of ones of the bit lines (36, 37, 28) {[0033]};
an outer electrode (27) on the dielectric layer (33 between 22 and 27) {[0035]}; and
an upper insulating layer (12) on top surfaces of the bit lines (36, 37, 28), a top surface of the dielectric layer (33 between 22 and 27), and a top surface of the outer electrode (27) {Fig. 21, orientation of Fig. 21 may be rotated 180 degrees to achieve claimed orientation; [0029], Base substrate 12 … may comprise dielectric material}.
Regarding claim 22, Liu teaches the three-dimensional memory device of claim 21, and Liu further teaches wherein the top surfaces (37/28) of the bit lines (36, 37, 28) directly contact a bottom surface of the upper insulating layer (12) {Fig. 21, orientation of Fig. 21 may be rotated 180 degrees to achieve claimed orientation; [0035]}.
Regarding claim 23, Liu teaches the three-dimensional memory device of claim 21, and Liu further teaches wherein a top surface of the dielectric layer (33 between 22 and 27) directly contacts a bottom surface of the upper insulating layer (12) {Fig. 21, orientation of Fig. 21 may be rotated 180 degrees to achieve claimed orientation}.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to claim 1 above, and further in view of Sel et al. (US20190034125A1).
Regarding claim 3, Liu teaches the three-dimensional memory device of claim 1, but Liu does not teach wherein the outer electrode is on top surfaces of the bit lines, and wherein the dielectric layer extends between the outer electrode and the top surfaces of the bit lines.
In an analogous art, Sel teaches in Fig. 3A and paragraph [0068, 0071, 0096] an outer electrode (306) is on top surfaces of bit lines (LBL), and wherein a dielectric layer (310) extends between the outer electrode (306) and the top surfaces of the bit lines (LBL) {the orientation of Fig. 3A may be rotated 180 degrees to match the claimed orientation}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu’s memory device based on the teachings of Sel – such that the outer electrode is on top surfaces of the bit lines, and wherein the dielectric layer extends between the outer electrode and the top surfaces of the bit lines – because all the claimed elements (e.g., outer electrode, bit lines, dielectric layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Sel) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 4, Liu as modified by Sel teaches the three-dimensional memory device of claim 3, and Liu further teaches wherein the dielectric layer (33 between 22 and 27) extends between the top surface of the stack structure (22, 33) and the outer electrode (27).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu.
Regarding claim 10, Liu teaches the three-dimensional memory device of claim 1, but Liu does not teach wherein the dielectric layer includes at least one of HfO, AlO, TiO, ZrO, or TaO.
However, Liu teaches in paragraph [0041] that TiO is a specific example of a dielectric. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu’s memory device based on the further teachings of Liu – such that the dielectric layer includes TiO – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to claim 21 above, and further in view of Hsu (US20240147688A1).
Regarding claim 24, Liu teaches the three-dimensional memory device of claim 21, but Liu does not teach wherein a bottom surface of the dielectric layer directly contacts the uppermost one of the interlayer insulating layers.
In an analogous art, Hsu teaches in Fig. 16A and paragraphs [0063, 0083, 0102] a bottom surface of a dielectric layer (105a) directly contacts an uppermost one (141) of the interlayer insulating layers (141, 144). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu’s memory device based on the teachings of Hsu – such that a bottom surface of the dielectric layer directly contacts the uppermost one of the interlayer insulating layers – because all the claimed elements (e.g., dielectric layer, interlayer insulating layers) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Hsu) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Villa et al. (US20220392527A1) teaches a memory array may be configured with conductive pillars that are each coupled with a respective set of memory cells, and may be selectively coupled with an access line. To support a dissipation or equalization of charge from unselected pillars, the memory array may be configured with a material layer or level that provides a dissipative coupling, such as a coupling having a relatively high resistance or a degree of capacitance, with a ground voltage or other voltage source (e.g., to support a passive equalization). Additionally, or alternatively, a memory array may be configured to support an active dissipation of accumulated charge or voltage by selectively coupling pillars that have been operated in a floating condition with a ground voltage or other voltage source (e.g., to perform a dynamic equalization).
Conclusion
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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