DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Invention I (Device), Species C, claims 1-11, in the reply filed on May 4, 2026 is acknowledged. Therefore, claims 1-11 are presented for examination.
Claim Objections
Claim 3 is objected to because of the following informalities:
In claim 3, “wherein the wherein the adhesive layer” should be amended with “wherein the adhesive layer”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, it is not clear what “position that is a same distance from the protective layer as the first electronic component” refers to, because Applicants do not specifically claim or define how the recited “same distance” is measured, which reference surface of the protective layer the distance is measured, and/or from which portion of the first electronic component and the adhesive layer the corresponding distances are determined, it remains unclear where the claimed position refers to.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5-8 and 10 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Miki (US 2017/0018533).
Regarding claim 1, Miki discloses a semiconductor device, comprising:
a wiring substrate (wiring substrate 5 or insulating layer 12/core substrate 10/insulating layer 12/lower solder resist layer 14, Fig. 19) with a first conductor portion (second wiring layer 22 in a center region, see Fig. 6) and a second conductor portion (second wiring layer 22 in left or right region, see Fig. 6) on a first surface (top surface of insulating layer 12 of the wiring substrate 5, Fig. 19, 6);
a protective film (upper solder resist layer 14, Fig. 19) on the first surface (top surface of 12, Fig. 19) of the wiring substrate (5, Fig. 19), the protective film (upper 14, Fig. 19) including a first opening (opening on the layer 14 having connection electrode in a center region, Fig. 19, 6) exposing the first conductor portion (22 in a center region of Fig. 19, 6), because the solder resist layer 14 includes openings exposing the second wiring layer 22 (Fig. 6) to be filled with the connection electrode CE during subsequent fabrication processes, and a second opening (opening on the layer 14 having connection electrode in left or right region, Fig. 19, 6) exposing the second conductor portion (22, Fig. 19, 6); Examiner notes that the recited first and second openings exposes the claimed first and second conductor portions during steps of fabrication processes and it is filled with different materials in later processes;
a first electronic component (first semiconductor chip 6, Fig. 19) mounted to the wiring substrate (5, Fig. 19), an electrode terminal (columnar electrode PE, Fig. 19) of the first electronic component (6, Fig. 19) connected to the first conductor portion (22, Fig. 19, 6) through the first opening (opening on the layer 14 having connection electrode in a center region, Fig. 19, 6), because the columnar electrode PE by Miki is electrically connected to the second wiring layer (22) through the openings having CE in the solder resist layer 14 (Fig. 19);
a second electronic component (semiconductor chip 7a, Fig. 19) stacked on the first electronic component (6, Fig. 19) via an adhesive layer (second underfill resin 32, Fig. 19);
a first resin layer (inner portion of first underfill 30, Fig. 19) between the protective film (upper 14, Fig. 19) and the first electronic component (6, Fig. 19), because Applicants do not specifically claim what material’s composition the first resin layer has, Applicants originally disclosed that “The second resin layer 8 is, for example, made of the same type resin material as the first resin layer 7” ([0041] of the present application), therefore, the claimed first and second resin layers may comprise different portions of a single, continuous resin material, in this case, the inner portion of first underfill 30 corresponds to the claimed first resin layer, while the outer portion of first underfill 30 corresponds to the claimed second resin layer;
a second resin layer (outer portion of first underfill 30, Fig. 19) between the protective film (upper 14, Fig. 19) and the adhesive layer (32, Fig. 19), the second resin layer (outer portion of 30, Fig. 19) being outside the first electronic component in a plan view, because the outer portion of the first underfill resin 30 covers outside the first semiconductor chip 6.
Furthermore, the limitations “first resin layer” and “second resin layer” are product-by-process limitations that do not structurally distinguish the claimed invention over the prior art, because (a) Applicant does not specifically claim what the first and second resin layers are formed of, (b) Applicant originally disclosed that the first and second resin layers can be made of the same type resin material ([0041] of the present application), and (c) therefore, without Applicants’ specifically claiming that the first and second resin layers are formed of different materials, the first and second resin layers can comprise a single, continuous resin material. Note that a product by process claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al, 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a product by process claim, and not the patentability of the process, and that an old or obvious product by a new method is not patentable as a product, whether claimed in product by process claims or not. Note that applicant has the burden of proof in such cases, as the above case law makes clear.
PNG
media_image1.png
1098
1429
media_image1.png
Greyscale
Regarding claim 5, Miki further discloses for the semiconductor device according to claim 1 that the second resin layer (outer portion of 30, Fig. 19) includes a portion extending beyond the adhesive layer (32, Fig. 19) in a plan view, because the outer portion of the first underfill 32 by Miki is laterally extended beyond second underfill resin 32 (Fig. 22).
Regarding claim 6, Miki further discloses for the semiconductor device according to claim 1 that the first resin layer (inner portion of 30, Fig. 19) fills a portion of the first opening (opening on the layer 14 having connection electrode in a center region, Fig. 19, 6), because Applicants do not specifically claim where “a portion of the first opening” positioned, the Merriam-Webster dictionary defines a word “portion” as “an often limited part of a whole”, and therefore, an arbitrary portion of the opening on the layer 14 can be selected for the claimed portion, in this case, an interface between the connection electrode CE and the solder resist layer 14 is filled with the inner portion of the first underfill reson 30 (Fig. 19).
Regarding claim 7, Miki further discloses for the semiconductor device according to claim 1 that the second resin layer (outer portion of 30, Fig. 19) fills a portion of the second opening (interface between the connection electrode CE and the opening on the layer 14 in left or right side of Fig. 19).
Regarding claim 8, Miki further discloses for the semiconductor device according to claim 1 that the first resin layer (inner portion of 30, Fig. 19) and the second resin layer (outer portion of 30, Fig. 19) are formed from a same resin material (first underfill resin, Fig. 19).
Regarding claim 10, Miki further discloses for the semiconductor device according to claim 1 that a portion of the second resin layer (a portion of the outer portion of 30, Fig. 19) covers an outer edge of the first electronic component (outer edge of 6, Fig. 19).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over by Miki (US 2017/0018533) in view of Shimizu (US 2010/0213605).
Regarding claim 3, Miki does not explicitly disclose that the adhesive layer is a die attached film.
However, Shimizu discloses that the semiconductor device includes the vertically stacked semiconductor chip assembly (Fig. 25), and the first electronic component 12 and the second electronic component 14 are attached to each other via the adhesive agent 59 (Fig. 25), which corresponds to the adhesive layer in the claimed invention, and Shimizu further discloses that the adhesive layer (59, Fig. 25) is a die attached film (die attach film, [0088]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the underfill resin by Miki with the die attach film disclosed by Shimizu to attach semiconductor chips, in order to achieve a more compact, high-density integrated circuit assembly and facilitate manufacturing processes by using a die attached film.
Claims 4, 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over by Miki (US 2017/0018533) in view of Kyozuka (US 2019/0029113).
Regarding claim 4, Miki does not explicitly disclose that the adhesive layer comprises an acrylate resin material, the first resin layer is an epoxy-based resin, and the second resin layer is an epoxy-based resin.
However, Kyozuka discloses that the electronic component device includes the underfill resin 74 filled into a gap between each semiconductor chip 70 and the wiring substrate 1, the sealing resin 76 filled between the lower wiring substrate 1 and upper wiring member UW, and the underfill resin 94 filled between the semiconductor chip 90 and wiring substrate 80 (Fig. 22), and therefore, the underfill resin 74 may correspond to the claimed first resin layer, the sealing resin 76 (labeled in Fig. 20) may correspond to the claimed second resin layer, and the underfill resin 94 may correspond to the claimed adhesive layer. Kyozuka further discloses that “the sealing resin 76 is, for example, is made of epoxy resin” (emphasis added, [0176]). Furthermore, Kyozuka further discloses various resin materials commonly used in a semiconductor package or assembly; for example, “the core layer 110 may be made of glass epoxy resin or the like” (emphasis added, [0066]), “examples of such insulating resin include epoxy resin, polyimide resin, etc.” (emphasis added, [0108]), and “photosensitive insulating resin including epoxy acrylate resin, phenol resin, polyimide resin or the like is used as the solder resist layer 42” (emphasis added, [0147]), and these teachings by Kyozuka demonstrate that epoxy-based resins and acrylate-containing resins are well known and widely used in semiconductor packaging structures, therefore, one of ordinary skill in the art would have recognized that the adhesive layer between the semiconductor components and the resin layer between the structural layers could be formed from epoxy-based resin or acrylate-containing epoxy resin, because such resin materials are conventionally employed for adhesion, insulation, and structural support in semiconductor packages or assemblies.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select an epoxy-based resin for the first resin layer and acrylate-containing resin material for the adhesive layer, as these resin materials are well-known alternatives used in semiconductor package structures, in order to provide suitable adhesion, processibility, and mechanical performance in semiconductor packages or assemblies.
Regarding claim 9, Miki in view of Kyozuka does not explicitly disclose that the first resin layer and the second resin layer have different compositions.
However, Kyozuka further discloses various resin materials commonly used in a semiconductor package or assembly; for example, “the core layer 110 may be made of glass epoxy resin or the like” (emphasis added, [0066]), “examples of such insulating resin include epoxy resin, polyimide resin, etc.” (emphasis added, [0108]), and “photosensitive insulating resin including epoxy acrylate resin, phenol resin, polyimide resin or the like is used as the solder resist layer 42” (emphasis added, [0147]), and these teachings by Kyozuka demonstrate that disclosed resins are well known and widely used in semiconductor packaging structures, therefore, one of ordinary skill in the art would have recognized that the resin layers between the semiconductor components and the structural layers could be selected from different resin compositions to satisfy desired physical, thermal or electrical properties of each resin layer in semiconductor packages or assemblies.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select different resin compositions for resin layers between semiconductor component and wiring substrate, as these resin materials are well-known alternatives used in semiconductor package structures, in order to optimize suitable adhesion, processibility, and mechanical performance in semiconductor packages or assemblies.
Regarding claim 11, Kyozuka further discloses that a portion of the second resin layer (76, Fig. 22, labeled in Fig. 20) is on an upper surface of the first electronic component (top surface of 70, Fig. 22).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WOO K LEE whose telephone number is (571)270-5816. The examiner can normally be reached Monday - Friday, 8:30 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815
Prosecution Insights