Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1, 3, AND 4 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection mailed on 09/23/2025. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/11/2025 has been entered.
Claim Interpretation
The Examiner has observed that even though claim 1 comprising preamble recites “a device for monitoring”, the term “device” lacks antecedent basis in the rest of claim 1 or any dependent claim currently filed. Thus, for the prior art considerations, the claims are treated as system claim reciting a black box with processor coupled to an optical via I2C bus, however is open-ended as the “electrically connected” could involve switches, multiplexers, inductors and so on. Furthermore, the Examiner does not give patentable weight to the adjective “anomaly” and just treats “anomaly detector” as a different type of “detector” that outputs an “error signal” when “timing duration reaches the preset time duration” (instant specification [0008], last sentence). However, the specification is silent to quantifiable value/dimension of “error signal” in terms of magnitude or the number of bits or if said signal is analogue/digital signal type.
In other words, there is a structure to such elements in claim 1 but deviates from the figures when said features do not define what constitutes as a type of “anomaly” or error or unexpected behavior as long as it observes such signals in a given timeframe/window/threshold.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, AND 4 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. (USPGPUB No. 2022/0069913 A1) in view of Divine et al. (US Pat No. 6081783 A, hereinafter referred to as Divine) and further in view of Pitigoi-Aaron al. (USPGPUB No. 2022/0091952 A1, hereinafter referred to as Pitigoi).
Referring to claim 1, Tanaka discloses a device for monitoring an inter-integrated circuit (I2C) bus {“communication of the I2C between the microcontroller 10 and the host controller 20a”, see Fig. 2, [0119], 2nd sentence} that is electrically connected between a processor {“the processor 100”, see Fig. 1b, 2, and 10 [0119], 2nd sentence} and an optical module {“optical transceiver is pluggable to any one of a [processor] first apparatus and a second apparatus and includes a clock recovery circuit”, see Figs. 2 and 3, see Abstract}, the I2C bus including a serial data (SDA) line {“Signals SCL and SDA are used for communication of the I2C”, see Fig. 3, [0119], 3rd sentence}, said device comprising:
a signal-edge detector electrically connected {“[signal-edge detector] microcontroller 10”, see Fig. 1a, [0108], 2nd sentence; the flexibility of “microcontroller 10” configured to detect either analogue or digital signals; the “edges” of the analog signal referring to the amplitude/apex of the sinusoidal wave; a digital signal “edge” refers to the signal cutoff transition from high-to-low activation or vice-versa} to the SDA line of the I2C bus {“extracts clock signals… from signals on individual lanes… from the main signal transmission circuit 21a [including SDA line]”, see Fig. 1b, [0077], 2nd sentence; the SDA line in question between “micro controller 10” correlates and passes the signals of the SDA line from “host controller 20b” (see Figures 1a and 1b}, and configured to continuously detect an SDA signal from the SDA line of the I2C bus {“Signals SCL and SDA are used for communication of the I2C”, see Fig. 3, [0119], 3rd sentence}, generate and output a timing-start signal {“[timing-start signal] control signal C_TRC, for the timing recovery circuits 110g1 to 110g4”, see Figs. 2 and 3, [0092], 1st sentence; the “micro controller 10” correlates and passes the signals of the SDA line from “host controller 20b” to the rest of “optical receiver 1” via “CDR circuit 110” and “CDR 120” respectively via “[timing-reset signal C_TRC] a message to and from the host controller 20a or the host controller 20b to which the microcontroller 10 is connected, through the bus 109 and the host communication circuit 103.” ([0144], see Fig. 1B)} when detecting that a logic level {step “ST3” per “sets operation configuration for the transmission circuit 11”, see Figs. 2, 3, and 13, [0174] last sentence} of the SDA signal changes from logical high to logical low {“switched to 100 G configuration or 200 G configuration in accordance with the transmission rate of the transmission apparatus”, see Figs. 2 and 3, [0108], 2nd sentence; such “transmission rate” of a SDA line that outputs a digital signal changes both from high to low and low to high depending active high/active low configuration “ADC 106 converts a monitor signal, which is input as an analog signal from the transmission circuit 11 and the reception circuit 12, into a digital signal” (see Figs. 1a or 1B, [0147])}, and generate and output a timing-reset signal {“the microcontroller 10 outputs the reset signal TxRST” (see Figs. 2 and 3, [0108], 3rd sentence) one of a plurality types of timing-reset signals including “RxRST” and “light emission stop signal TxDIS” ([0109])} when detecting that the logic level of the SDA signal changes from logical low to logical high {“after [logical level changes] configuration is switched, the CDR circuit 110 operates with an operation configuration corresponding to the transmission rate set values”, see Figs. 2 and 3, [0108]};
an anomaly detector electrically connected to said signal-edge detector {“a message to and from the host controller 20a or the host controller 20b to which the microcontroller 10 is connected, through the bus 109 and the host communication circuit 103” ([0144], see Fig. 1B) in that message from the signal-edge detector “microcontroller 10” connects to anomaly detector “CDR circuit 110 [detects] extracts clock signals” or any given behavior or misbehavior of the clock signals, see Fig. 2, [0077], 2nd sentence;}, and configured to upon receiving the timing-start signal from said signal-edge detector {“in accordance [upon receiving] with the control signal [timing-start] C_TRC”, see Figs. 2and 3, [0092], 2nd sentence}, start to time a timing duration {“control circuit 110d sets, … [starts a timing duration] frequencies of the oscillators inside the PLL circuits”, see Figs. 2 and 3, [0092], 2nd sentence}, and determine whether the timing duration reaches a preset time duration {preset time duration “period has arrived? Step St6”, see Fig. 13, [0179]}, generate and output an error signal {“ processing for outputting an [error signal] alarm and a warning”, see Fig. 13, [0187]} when it is determined that the timing duration reaches the preset time duration {“the case where the period has arrived Yes in step St6”, see Fig. 13, [0179], last sentence}, and upon receiving the timing-reset signal from said signal-edge detector {“[upon receiving] in accordance with a reset signal TxRST”, see Figs. 13 and 14, [0196]; or similar response for “outputs a reset signal RxRST to the CDR circuit 120”, [0112]}, reset the timing duration to zero {“resets the [timing duration of] CDR circuit 110 and the CDR circuit 120 in accordance with a reset signal TxRST”, see Fig. 14, [0196], [0112]};
and a reset-interrupt generator electrically connected to said anomaly detector {“processor 100” generator component producing “ResetL becomes Low level, interruption [generation] occurs in the processor 100” ([0191], 1st sentence) is coupled to anomaly detector “CDR 110” (see Fig. 2, [0077])}, adapted to be electrically connected to the processor and the optical module {“the interrupt process illustrated in the flowchart of FIG. 14 in accordance with the occurrence of the interruption”, see Fig. 14, [0191]}, and configured to in response to receipt of the error signal from said anomaly detector {anomaly detector CDR circuit 110 “outputting an alarm and a warning on the basis of results of the processing from the steps St8 to St11” in particular “step St12”, see Fig. 13, [0187]}, perform one of a step of outputting an interrupt signal to the processor {the same step St12 performing outputting interrupt signal “performs the interrupt process illustrated in the flowchart of FIG. 14 in accordance with the occurrence of the interruption.”, see Fig. 14, [0191]} to allow the processor to remove an abnormal state {“In the case where abnormality of the transmission circuit 11 and the reception circuit 12 is detected,”, see Fig. 1b, [0076], 2nd sentence; “abnormal transmission of a transmission optical signal TxS is prevented [/removed]”, [0109], last sentence}, and a step of outputting a pin-reset signal to the optical module {pin-reset signal “reset signal TxRST” or a “reset signal RxRST” to the appropriate receiver/transmitter components of the optical module “optical transceiver 1” (see Fig. 10, [0142], [0112])} to allow the optical module to reset a pin {“low power consumption mode, for example, in the case where a main signal is not transmitted or received [on a pin/lane], to the microcontroller 10” (see Fig. 1b, [0076] last sentence) when LPM Mode “operate in a low power consumption mode” along with resetting a pin from high voltage to low ([0076], last sentence); another pin reset example “after reset is performed, the CDR circuit 120 operates with an operation configuration based on a program with high priority” (see Figs. 1a, 1b, 2, [0112])} that is electrically connected to the SDA line of the I2C bus {“from signals on individual lanes of the transmission data signal TxDATAa or TxDATAb from the main signal transmission circuit 21a”, see Fig. 1b, [0077], 2nd sentence}.
Tanaka does not appear to explicitly disclose a signal-edge detector electrically connected to the SDA line of the I2C bus, and configured to continuously detect an SDA signal from the SDA line of the I2C bus;
However, Divine discloses a signal-edge detector electrically connected {signal-edge detector “host interface 301, the primary components of which are serial control port 3201, (general purpose I/O port 3202, and parallel port 3203”, see Fig. 32, Col 55, lines 17-19} to the SDA line of the I2C bus {“I2C operation the SCL/SCK, SDA, and INTREQ signals are used.”, see Figs. 32 and 33, Col 59, lines 54-56}, and configured to continuously detect an SDA signal from the SDA line of the I2C bus {“I2C operation the SCL/SCK, SDA, and INTREQ signals are used. SCL/SCK (pin A0) is the serial clock input that is [continuously detect] always driven by an external device.”, see Figs. 32 and 33, Col 59, lines 54-56}.
Tanaka and Divine are analogous art because they are from the same problem-solving area, method and systems for handling I2C devices.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Tanaka and Divine before him or her, to modify Tanaka’s “processor 100” (see Figs. 2) incorporating Divine’ “host interface 301” (see Fig. 32, Col 55).
The suggestion/motivation for doing so would have been to implement an digital audio decoder which provides maximum utility and flexibility in view of the array of different formats and interfaces while also being able to perform additional functions appropriate to a digital audio system decoder (Divine Col 2, lines 17-25).
Therefore, it would have been obvious to combine Divine with Tanaka to obtain the invention as specified in the instant claim(s).
However, neither Tanaka or Divine appears to explicitly disclose upon receiving the timing-start signal from said signal-edge detector, count a counted value from zero based on a reference clock signal, and generate and output a timeout signal every time overflow occurs in said counter during counting, and upon receiving the timing-reset signal from said signal-edge detector, reset the counted value: and a determining module that is electrically connected to said signal-edge detector, said counter and said reset-interrupt generator, and that is configured to:
receive the timeout signal from said counter, count a number of accumulative times of receiving the timeout signal from said counter,
determine whether the timing duration reaches the preset time duration by determining whether the number of accumulative times of receiving the timeout signal from said counter has reached a preset number, generate and output the error signal to said reset-interrupt generator when it is determined that the number of accumulative times of receiving the timeout signal from said counter has reached the preset number, and upon receiving the timing-reset signal from said signal-edge detector, reset the number of accumulative times of receiving the timeout signal to zero.;
However, Pitigoi discloses upon receiving the timing-start signal from said signal-edge detector {“start condition 406”, see Fig. 4 [0055]}, count a counted value {“[number of] Transitions on the Data wire”, see Fig. 5 [0056], last sentence} from zero based on a reference clock signal {“transmits a clock signal on the SCL wire 404.”, see Fig. 4 [0055]}, and generate and output a timeout signal {“lack of response as a [timeout] NACK”, see Fig. 4 [0055]} every time overflow occurs in said counter during counting {“ Frame synchronization can be problematic in [overflow] high-data rate or noisy bus environment”, see Figs. 4 and 5 [0082], 1st sentence}, and upon receiving the timing-reset signal from said signal-edge detector {“an edge 1212 on SCL 1204 validates the restart and may trigger a receiver to capture current state of SDA 1202”, see Fig. 12 [0087], last sentence}, reset the counted value {“SCL 1204 to reset [the counted value] or configure receiving circuits prior to the appearance of a next command word 1214 on the serial bus”, see Fig. 12 [0087], last sentence}:
and a determining module {“adapted to enable a [determining module] receiver to safely intervene when an error is detected”, see Fig. 12 [0086]} that is electrically connected to said signal-edge detector {“Certain of these procedures and adaptations are described with reference to a 2-line serial bus [electrically connected]” as claimed, see Fig. 12 [0086], last sentence}, said counter and said reset-interrupt generator {“[reset-interrupt generator component of respective] sender and receiver may establish a contract governing the use and format of an error signaling window”, see Fig. 12 [0085]}, and that is configured to:
receive the timeout signal from said counter {“an edge 1212 on SCL 1204 validates the restart and may trigger a receiver to capture current state of SDA 1202”, see Fig. 12 [0087], last sentence}, count a number of accumulative times of receiving the timeout signal from said counter {number of accumulative times as claimed “corresponds to transmission of a sequence of symbols that include three or more consecutive symbols 1208 with a value of ‘2’”, see Fig. 12 [0087]}, determine whether the timing duration reaches the preset time duration {“operation and configuration of [time duration] error signaling windows may be defined during system design [presets]”, see Fig. 12 [0085]} by determining whether the number of accumulative times {“establish a contract governing the use and format [of accumulative times] of an error signaling window”, see Fig. 12 [0085]} of receiving the timeout signal {“[timeout signal] Error signaling windows can be used in data transfer”, see Fig. 12 [0086], 1st sentence} from said counter has reached a preset number {“when timing closure approaches its [preset number] specified limits”, see Fig. 12 [0086]}, generate and output the error signal to said reset-interrupt generator {“[outputted] error signaling window identifier 1226”, see Fig. 12 [0088]} when it is determined that the number of accumulative times of receiving the timeout signal {“pattern 1206 corresponds to transmission of a sequence of symbols”, see Fig. 12 [0087]} from said counter has reached the preset number {“the sequence of symbols causes SCL 1204 to be held [at a preset number] in a low signaling state 1210 while SDA 1202 toggle”, see Fig. 12 [0087]}, and upon receiving the timing-reset signal from said signal-edge detector {“an edge 1212 on SCL 1204 validates the restart and may trigger a receiver to capture current state of SDA 1202”, see Fig. 12 [0087], last sentence}, reset the number of accumulative times of receiving the timeout signal to zero {“SCL 1204 to reset [the counted value] or configure receiving circuits prior to the appearance of a next command word 1214 on the serial bus”, see Fig. 12 [0087], last sentence}.
Tanaka/Divine and Pitigoi are analogous art because they are from the same problem-solving area, method and systems for handling I2C devices.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Tanaka/Divine and Pitigoi before him or her, to modify Tanaka/Divine’s device incorporating Pitigoi’s “signaling adaptation (see Fig. 12, [0025]).
The suggestion/motivation for doing so would have been to implement appropriate error signaling windows can be used in data transfer to and from a bus master or between slave devices which in turn achieves robust error identification and ensure that serial can operate reliably when timing closure approaches its specified limits ([0086], 1st and 2nd sentences).
Therefore, it would have been obvious to combine Pitigoi with Tanaka/Divine to obtain the invention as specified in the instant claim(s).
As per claim 3, the rejection of claim 2 is incorporated and Tanaka discloses wherein the preset time duration is related to a period of the reference clock signal {“starts up the timer of the timer circuit 105 (step St5)” where the processor 100 starts with a system clock or “quartz crystal” depending on the processor manufacturer, see Fig. 13, [0178]}, a maximum setting of said counter and the preset number {“Regarding setting for the timing recovery circuits 110g1 to 110g4, types of signals”, see Fig. 13, [0101]}.
As per claim 4, the rejection of claim 3 is incorporated and Tanaka discloses wherein the preset time duration is a product of the period of the reference clock signal {“starts up the timer of the timer circuit 105 (step St5)” where the processor 100 starts with a system clock or “quartz crystal” depending on the processor manufacturer, see Fig. 13, [0178]}, the maximum setting of said counter and the preset number {“Regarding setting for the timing recovery circuits 110g1 to 110g4, types of signals”, see Fig. 13, [0101]}.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references are applicable as 103 art teaching at least one limitation recited in claim 1: US 20240111619 A1, US 20200004708 A1, US 20180181531 A1, and US 20140149615 A1.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C. B./
Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184