DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on December 12, 2023 and IDS filed on March 20, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDSs are considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 5-9 and 12-14 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Chen et al. US 2022/0131004.
Regarding claim 1, Chen teaches a semiconductor structure (e.g., Fig. 11, [32]-[34]; also see Figs. 2-10 and the description thereof for more details) comprising:
a transistor (e.g., transistor including 230S and 230D, Fig. 11) comprising a first source/drain region (e.g., 230S, Fig. 11) located on a first side of a gate structure (e.g., 250, Fig. 11) and a second source/drain region (e.g., 230D, Fig. 11) located on a second side of the gate structure;
a backside dielectric cap (e.g., 290, Fig. 11E) in direct physical contact with a surface of the gate structure; and
a backside source/drain contact structure (e.g., 270, Fig. 11C) directly contacting a surface of the first source/drain region of the transistor.
Regarding claim 2, Chen teaches the semiconductor structure of Claim 1, wherein the backside dielectric cap prevents the backside source/drain contact structure from directly contacting the gate structure (e.g., Fig. 11C).
Regarding claim 5, Chen teaches the semiconductor structure of Claim 1, further comprising a gate spacer (e.g., 216, Fig. 11C) located along a sidewall of the gate structure and a sidewall of the backside dielectric cap.
Regarding claim 6, Chen teaches the semiconductor structure of Claim 1, wherein the second source/drain region is located on a surface of a backside source/drain contact placeholder structure (e.g., 294, Fig. 11C).
Regarding claim 7, Chen teaches the semiconductor structure of Claim 1, further comprising a backside interlayer dielectric layer (e.g., 294, Fig. 11) embedding the backside source/drain contact structure and a shallow trench isolation structure (e.g., 204, Fig. 11) that is present beneath the backside dielectric cap.
Regarding claim 8, Chen teaches the semiconductor structure of Claim 7, further comprising a backside power system (e.g., 292, Fig. 11C) located on the backside interlayer dielectric layer and contacting the backside source/drain contact structure.
Regarding claim 9, Chen teaches the semiconductor structure of Claim 1, wherein the first source/drain region, the second source/drain region and the gate structure are embedded in a frontside middle-of-the-line (MOL) layer (e.g., 260, Fig. 11)
Regarding claim 12, Chen teaches the semiconductor structure of Claim 1, wherein the transistor is a nanosheet transistor comprises a plurality of spaced apart semiconductor channel material nanosheets (e.g., 208, Fig. 11C, Fig, 11E), wherein the gate structure wraps around each of the spaced apart semiconductor channel material nanosheets (e.g., Fig. 11E).
Regarding claim 13, Chen teaches the semiconductor structure of Claim 12, wherein the nanosheet transistor is located on a surface of a bottom dielectric isolation layer (e.g., 256, Fig. 11).
Regarding claim 14, Chen teaches the semiconductor structure of Claim 13, wherein the bottom dielectric isolation layer is located adjacent to the backside dielectric cap (e.g., Fig. 11).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 4 are rejected are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. US 2022/0131004 in view of Bao et al. US 2023/0009977.
Regarding claim 3, Chen teaches the semiconductor structure of Claim 1 as discussed above.
Chen does not explicitly teach wherein the backside source/drain contact structure has a first portion having a first critical dimension, CD1, and a second portion having a second critical dimension, CD2, wherein CD2 is smaller than CD1, and wherein the second portion of the backside source/drain contact structure is closest to the first source/drain region than the first portion of the backside source/drain contact structure.
Bao teaches that wherein the backside source/drain contact structure has a first portion having a first critical dimension, CD1 (e.g., first portion of 116, disposed in a region far from the source/drain region 108, Fig. 1B), and a second portion having a second critical dimension, CD2 (e.g., second portion of 116, disposed in a region close to the source/drain region 108, Fig. 1B), wherein CD2 is smaller than CD1 (e.g., Fig. 1B), and wherein the second portion of the backside source/drain contact structure is closest to the first source/drain region (e.g., 108 having CD1, Fig. 11B) than the first portion of the backside source/drain contact structure (e.g., Fig. 1B).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Chen to include wherein the backside source/drain contact structure has a first portion having a first critical dimension, CD1, and a second portion having a second critical dimension, CD2, wherein CD2 is smaller than CD1, and wherein the second portion of the backside source/drain contact structure is closest to the first source/drain region than the first portion of the backside source/drain contact structure for the purpose of reducing the contact resistance between the source/drain region and source/drain contact structure for example (e.g., Bao, [26]).
Regarding claim 4, Chen in view of Bao teaches the semiconductor structure of Claim 3, wherein the second portion of the backside source/drain contact structure having CD2 has sidewalls that are substantially vertically aligned to sidewalls of the first source/drain region (e.g., Bao, Fig. 1B).
Allowable Subject Matter
Claims 10, 11 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 16-20 are allowed at this time, pending updated search before the Examiner's next response, because the prior art of record neither anticipates nor render obvious the limitation of the base claim 16 that recites “forming a shallow trench isolation structure in a semiconductor substrate and adjacent to a mesa portion of a semiconductor substrate, wherein a semiconductor channel material structure is located on the mesa portion of the semiconductor substrate; forming a dielectric layer on the shallow trench isolation structure and on top of the semiconductor channel material structure; selectively removing the dielectric layer that is located on top of the semiconductor channel material structure, while maintaining the dielectric layer on the shallow trench isolation structure; forming a sacrificial gate structure on the semiconductor channel material structure; forming a backside source/drain contact placeholder structure in the semiconductor substrate and on each side of the sacrificial gate structure; forming a source/drain region on each of the backside source/drain contact placeholder structures; replacing the sacrificial gate structure with a gate structure; removing the semiconductor substrate to physically expose each of the backside source/drain contact placeholder structures; forming a backside interlayer dielectric layer embedding each of the backside source/drain contact placeholder structures; and replacing at least one of the backside source/drain contact placeholder structures with a backside source/drain contact structure” in combination with other elements of the base claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bo Bin Jang whose telephone number is (571) 270-0271. The examiner can normally be reached on M-F from 9:00 AM to 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BO B JANG/Primary Examiner, Art Unit 2818 January 29, 2026