DETAILED ACTION
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Election/Restrictions
Applicant’s election without traverse of species A, reflected in claims 1-11 in the reply filed on 06/25/2026 is acknowledged. Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142 (b), as being drawn to the nonelected group.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 20240379679 A1, hereinafter Li’679) in view of KWON et al. (US 20230326926 A1, hereinafter Kwon’926).
Regarding independent claim 1, Li’679 teaches, “A semiconductor structure (fig. 1-9; ¶ [0001] - ¶ [0157]) comprising:
a first forksheet transistor (102X) comprising a plurality of spaced apart and vertically stacked first semiconductor channel material nanosheets (126), and a first gate structure (116, 130A, 130B, 132, 134, 136) contacting each of the first semiconductor channel material nanosheets (126), wherein the first gate structure comprises a first gate electrode (130A, 130B, 132, 134) and each first semiconductor channel material nanosheet (126) has a first length;
a second forksheet transistor (102Y) located above the first forksheet transistor and comprising a plurality of spaced apart and vertically stacked second semiconductor channel material nanosheets (108), and a second gate structure (116, 112A, 112B, 132, 134, 136) contacting each of the second semiconductor channel material nanosheets (108), wherein the second gate structure comprises a second gate electrode (112A, 112B, 132, 134) and each second semiconductor channel material nanosheet (108) has a second length ((that is less than the first length));
a middle dielectric isolation layer (124) separating a bottommost second semiconductor channel material nanosheet of the spaced apart and vertically stacked second semiconductor channel material nanosheets from a topmost first semiconductor channel material nanosheet of the spaced apart and vertically stacked first semiconductor channel material nanosheets; and
a frontside gate cut structure (106) located adjacent to the second forksheet transistor (102Y) and located over the middle dielectric isolation layer (124), wherein the frontside gate cut structure (106, along with bonding layer 124) electrically isolates the first gate electrode (130A, 130B, 132, 134) from the second gate electrode (112A, 112B, 132, 134)”.
But Li’679 is silent upon the provision of wherein the second length is less than the first length.
However, Kwon’926 teaches a similar vertical stack semiconductor device (fig. 2A-2D), the second length (222) is less than the first length (212).
Li’679 and Kwon’926 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Li’679 with the features of Kwon’926 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Li’679 and Kwon’926 to include nanosheets of the upper channel layer smaller length than the same of the lower channel layer according to the teachings of Kwon’926, which ‘ enable the multi-stack semiconductor device 20 to have a reduced number of contact structures which connect the lower and upper field-effect transistors 210 and 220 to one or more voltage sources and other circuit elements’. See Kwon’926, ¶ [0062].
Regarding claim 2, Li’679 modified with Kwon’926 further teaches, “The semiconductor structure of Claim 1, further comprising a dielectric wall structure (138, 140) contacting (indirectly) a sidewall of each first semiconductor channel material nanosheet, the middle dielectric isolation layer, and each second semiconductor channel material nanosheet”.
Allowable Subject Matter
Claims 3-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding dependent claim 3 and 8, the prior arts of record do not anticipate or make obvious, inter alia, the feature of: a frontside contact structure passing through the frontside gate cut structure.
The other dependent claims are also objected as they depend on the objected claims 3 and 8.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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