DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lilak et al. (U.S. Patent No. 11,664,373).
Regarding to claim 1, Lilak teaches a semiconductor device comprising:
a first stacked field-effect transistor structure comprising a first lower field-effect transistor device and a first upper field-effect transistor device (Fig. 4, first stacked field-effect transistor structure comprising first lower field-effect transistor device 410 and first upper field-effect transistor device 430); and
a second stacked field-effect transistor structure comprising a second lower field-effect transistor device and a second upper field-effect transistor device (Fig. 4, second stacked field-effect transistor structure comprising second lower field-effect transistor device 460 and second upper field-effect transistor device 480);
wherein at least one of: the first lower field-effect transistor device comprises a different number of channel layers than the second lower field-effect transistor device; and the first upper field-effect transistor device comprises a different number of channel layers than the second upper field-effect transistor device (Fig. 4, the first lower field-effect transistor device comprises 1 channel layer, the second lower field-effect transistor device comprises 3 channel layers; the first upper field-effect transistor device comprises 1 channel layer, the second upper field-effect transistor device comprises 2 channel layers).
Regarding to claim 2, Lilak teaches the first lower field-effect transistor and the first upper field-effect transistor device comprise a same number of channel layers (Fig. 1, the first lower field-effect transistor and the first upper field-effect transistor device both comprise 1 channel layer, noted that the first lower field-effect transistor comprises two channels in same layers).
Regarding to claim 3, Lilak teaches at least some of the channel layers in the first stacked field-effect transistor structure have different widths (Fig. 4).
Regarding to claim 4, Lilak teaches at least one of the first and second upper field-effect transistor devices comprises at least one first upper channel layer and at least one second upper channel layer having different widths (Fig. 4, the first and second upper field-effect transistor devices comprises first upper channel layer 431 and second upper channel layer 481 having different widths).
Regarding to claim 5, Lilak teaches least one of the first and second lower field-effect transistor devices comprises at least one first lower channel layer and at least one second lower channel layer having different widths (Fig. 4, the first and second lower field-effect transistor devices comprises first lower channel layer 411 and second lower channel layer 461 having different widths).
Regarding to claim 6, Lilak teaches the channel layers corresponding to the first upper field-effect transistor device, the channel layers corresponding to the first lower field-effect transistor device, and an isolation layer disposed between the first lower field-effect transistor device and the first upper field-effect transistor device are alternately stacked with a plurality of gate structures of the first stacked field-effect transistor structure (Fig. 4, isolation layer 455 disposed between upper gate structure 433 and lower gate structure 413).
Regarding to claim 7, Lilak teaches a semiconductor device comprising:
a plurality of stacked device structures comprising two or more upper devices, each comprising one or more upper channel layers, and two or more lower devices, each comprising one or more lower channel layers (Fig. 4, two stacked device structures comprising two upper devices, each comprising one or more upper channel layers, and two lower devices, each comprising one or more lower channel layers);
wherein a first number of upper channel layers of a first one of the two or more upper devices is different than a second number of upper channel layers of a second one of the two or more upper devices (first number of upper channel layers of the first upper device is 1, different than the second number upper channel layers of the second upper device, which is 2); and
wherein a third number of lower channel layers of a first one of the two or more lower devices is different than a fourth number of lower channel layers of a second one of the two or more lower devices (Fig. 4, third number of lower channel layers of the first lower devices is 1, different than a fourth number of lower channel layers of the second lower device, which is 3).
Regarding to claim 8, Lilak teaches at least one of the upper devices comprises at least one first upper channel layer and at least one second upper channel layer having different widths (Fig. 4, the upper devices comprise one first upper channel layer 431 and one second upper channel layer 481 having different widths).
Regarding to claim 9, Lilak teaches at least one of the lower devices comprises at least one first lower channel layer and at least one second lower channel layer having different widths (Fig. 4, the lower devices comprise first lower channel layer 411 and second lower channel layer 461 having different widths).
Regarding to claim 10, Lilak teaches a given one of the stacked device structures comprises an isolation layer disposed between the one or more upper devices and the one or more lower devices of the given stacked device structure (Fig. 4, element 455).
Regarding to claim 11, Lilak teaches the first and second upper devices and the first and second lower devices comprise respective field-effect transistor devices (column 2, line 30).
Regarding to claim 12, Lilak teaches the first and second upper devices and the first and second lower devices comprise respective nanosheet field-effect transistor devices (column 2, line 31).
Regarding to claim 13, Lilak teaches a first stacked device structure and a second stacked device structure provide a complementary field-effect transistor structure (column 8, lines 20-22, lines 33-35, upper and lower MOS devices have opposite types).
Regarding to claim 14, Lilak teaches one of the first upper device and the first lower device in the first stacked device structure comprises an n-type field-effect transistor device and the other one of the first upper device and the second lower device in the first stacked device structure comprises a p-type field-effect transistor device (column 8, lines 20-22, lines 33-35).
Claims 15 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ando et al. (U.S. Patent No. 10,734,447).
Regarding to claim 15, Ando teaches a method comprising:
forming first and second stacked field-effect transistor device structures, each of the first and second stacked field-effect transistor device structures comprising a plurality of channel layers corresponding to an upper field-effect transistor device and a lower field-effect transistor device (Fig. 4, left and right stacked field-effect transistor device structures, each comprising a plurality of channel layers corresponding to an upper field-effect transistor device and a lower field-effect transistor device); and
removing at least one channel layer from the plurality of channel layers of the first stacked field-effect transistor device structure, wherein the removing results in at least one of: a first number of channel layers of the lower field-effect transistor device corresponding to the first stacked field-effect transistor device structure being different than a second number of channel layers of the lower field-effect transistor device corresponding to the second stacked field-effect transistor device structure; and a third number of channel layers of the upper field-effect transistor device corresponding to the first stacked field-effect transistor device structure being different than a fourth number of channel layers of the upper field-effect transistor device corresponding to the second stacked field-effect transistor device structure (Fig. 7, column 11, lines 20-24, removing channel layer from the first stacked field-effect transistor device structure 106, the removing results in a number of channel layers of the upper field-effect transistor device corresponding to the first stacked field-effect transistor device structure 106 being different than a number of channel layers of the upper field-effect transistor device corresponding to the second stacked field-effect transistor device structure 102).
Regarding to claim 20, Ando teaches the lower field-effect transistor devices comprise one of n-type field-effect transistor devices and p-type field-effect transistor devices, and the upper field-effect transistor devices comprise the other one of the n-type field-effect transistor devices and the p-type field-effect transistor devices (column 4, lines 4-9).
Claims 15-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tsao (U.S. Patent No. 11,532,617).
Regarding to claim 15, Tsao teaches a method comprising:
forming first and second stacked field-effect transistor device structures, each of the first and second stacked field-effect transistor device structures comprising a plurality of channel layers corresponding to an upper field-effect transistor device and a lower field-effect transistor device (Fig. 9, left and right stacked field-effect transistor device structures, each comprising plurality of channel layers 12-2 and 12-3 corresponding to upper field-effect transistor device and 12-1 corresponding to lower field-effect transistor device); and
removing at least one channel layer from the plurality of channel layers of the first stacked field-effect transistor device structure, wherein the removing results in at least one of: a first number of channel layers of the lower field-effect transistor device corresponding to the first stacked field-effect transistor device structure being different than a second number of channel layers of the lower field-effect transistor device corresponding to the second stacked field-effect transistor device structure; and a third number of channel layers of the upper field-effect transistor device corresponding to the first stacked field-effect transistor device structure being different than a fourth number of channel layers of the upper field-effect transistor device corresponding to the second stacked field-effect transistor device structure (Figs. 10-11, column 18, lines 22-24, removing channel layer from the first stacked field-effect transistor device structure, the removing results in a number of channel layers of the upper field-effect transistor device corresponding to the first stacked field-effect transistor device structure being different than a number of channel layers of the upper field-effect transistor device corresponding to the second stacked field-effect transistor device structure).
Regarding to claim 16, Tsao teaches removing the at least one channel layer from the plurality of layers of the first stacked field-effect transistor device structure comprises: forming a mask layer to cover at least the upper field-effect transistor device of the second stacked field-effect transistor device structure (Fig. 9, element 27; column 11, lines 30-33); performing a first etching process that etches through the at least one channel layer, corresponding to the upper field-effect transistor device of the first stacked field-effect transistor device structure (Figs 10-11); and performing a second etching process to remove at least the mask layer (Fig. 11, the mask has been removed).
Regarding to claim 17, Tsao teaches forming a gate stack layer around the remaining channel layers of the first and second stacked field-effect transistor device structures (Fig. 13, element 296, column 13, line 20).
Regarding to claim 18, Tsao teaches removing the at least one channel layer from the plurality of channel layers of the first stacked field-effect transistor device structure comprises: forming a mask layer to cover at least the lower field-effect transistor device of the second stacked field-effect transistor device structure (Fig. 9, element 27; column 11, lines 30-33); performing a first etching process that etches through a portion of a gate stack layer and the at least one channel layer corresponding to the lower field-effect transistor device of the first stacked field-effect transistor device structure (Figs 10-11); and performing a second etching process to remove at least the mask layer (Fig. 13, the mask has been removed).
Regarding to claim 19, Tsao teaches forming a dielectric layer that covers exposed portions of the gate stack layer of the first stacked field-effect transistor device structure and a gate stack layer of the first stacked field-effect transistor device structure resulting from the first and second etching processes (Fig. 14; column 14, lines 22-26).
Pertinent Art
For the benefits of the Applicant, US-20230343823-A1, US-10700064-B1, US-10879352-B2, US-10381438-B2, US-12294005-B2, US-20210233909-A1, US-10101359-B2, US-20220044973-A1, US-10886368-B2, and US-11158544-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. The references fail to disclose the limitations including “removing at least one channel layer from the plurality of channel layers of the first stacked field-effect transistor device structure, wherein the removing results in at least one of: a first number of channel layers of the lower field-effect transistor device corresponding to the first stacked field-effect transistor device structure being different than a second number of channel layers of the lower field-effect transistor device corresponding to the second stacked field-effect transistor device structure; and a third number of channel layers of the upper field-effect transistor device corresponding to the first stacked field-effect transistor device structure being different than a fourth number of channel layers of the upper field-effect transistor device corresponding to the second stacked field-effect transistor device structure.”
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897