DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/12/2023 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract is consistent with the requirements set forth in the MPEP 608.01(b).
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: METHOD OF MANUFACTURING AN ELECTRONIC DEVICE COMPRISING ELECTROPOLISHING
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 12, the phrase "for example" and “preferable” in line 2, renders the claim indefinite because it is unclear whether the limitation(s) following the phrase are part of the claimed invention. See MPEP § 2173.05(d). For examination purposes, the limitation “wherein the first layer has a doping level strictly lower, for example at least ten times lower, preferably at least a thousand times lower, than the sacrificial layer” is being interpreted as “wherein the first layer has a doping level strictly lower, by ten time lower to a thousand times lower, than the sacrificial layer.” Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-5, 8, 10 and 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hwang et al. US PGPub. 2017/0236807. Regarding claim 1, Hwang teaches a method (fig. 1) [0020] of manufacturing an electronic device (fig. 5) [0024] comprising the following successive steps: a) forming (steps 100-102, fig. 1) a structure (fig. 3) [0022] comprising a diode stack (206+208+210, fig. 3) [0042] disposed on a first substrate (200, fig. 3) [0043], and a sacrificial layer (204, fig.3) [0046] of semiconductor material (InGan/GaN, [0042]) interposed between the first substrate (200) and the diode stack (206+208+210); b) transferring (steps 104-106, fig. 1) the structure (fig. 3) to a second substrate (408, fig. 4) [0051]; and c) removing (step 108, fig. 1) the first substrate (200) by electropolishing (fig. 4; [0051]) the sacrificial layer (204) by applying a bias voltage (402, fig. 4) [0051] to the sacrificial layer (204) via the diode stack (206+208+210) (Hwang et al., fig. 1-5).
Regarding claim 3, Hwang teaches the method according to claim 1, wherein, in step c), the structure (fig. 3) is immersed in an electrolyte (406, fig. 4) [0051] (Hwang et al., fig. 4, [0051]).
Regarding claim 4, Hwang teaches the method according to claim 3, wherein, in step c), the bias voltage (402)is applied between a first electrode (304, fig. 4) [0045] (indirectly through 202, 204, 206, 208, and 210, fig. 4) connected to a conductive (300, fig. 4) [0050] layer disposed on the second substrate (408), and a second electrode (404, fig. 4) [0051] immersed in the electrolyte (406) (Hwang et al., fig. 4, [0051]).
Regarding claim 5, Hwang teaches the method according to claim 4, wherein the conductive layer (300) coats (at least covers a portion of) the second substrate (408) (Hwang et al., fig. 4).
Regarding claim 8, Hwang teaches the method according to claim 1, wherein, in step a), the first substrate (200) is a full wafer with a maximum lateral dimension strictly smaller (see fig. 4) than that of the second substrate (408) (Hwang et al., fig. 4).
Regarding claim 10, Hwang teaches the method according to claim 1, wherein the diode stack (206+208+210) comprises: a first layer (206, fig. 3) [0042] doped with a first type of conductivity (n-GaN, [0042]) coating the sacrificial layer (204); an active layer (208, fig. 3) [0042] coating the first layer (206); and a second layer (210, fig. 3) [0042] doped with a second type of conductivity (p-GaN, [0042]), opposite the first type of conductivity (n-GaN), coating the active layer (208) (Hwang et al., fig. 3).
Regarding claim 13, Hwang teaches the method according to claim 1, wherein the sacrificial layer (204) is made of an III-V semiconductor material (InGaN/GaN, [0042]) (Hwang et al., [0042]). Regarding claim 14, Hwang teaches the method according to claim 1, wherein the sacrificial layer (204) is made of gallium nitride(InGaN/GaN, [0042]) (Hwang et al., [0042]).
Regarding claim 15, Hwang teaches the method according to claim 1, wherein the diode stack (206+208+210) is an inorganic light-emitting diode stack (micro-LED devices, [0045], [0062]) (Hwang et al., fig. 3, [0045], [0062]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. US PGPub. 2017/0236807 as applied to claim 1 above, and further in view of Robin et al. US PGPub. 2022/0320367. Regarding claim 2, Hwang teaches the method according to claim 1, wherein, in step b), transferring is performed by flip-chip bonding [0017] on the side of a first (top face in fig. 3; bottom face in fig. 4) face of the diode stack (206+208+210) opposite the first substrate (200) (Hwang et al., fig. 3-4). But Hwang fails to teach wherein transferring is performed by conductive molecular bonding. However, Robin teaches a method of manufacturing an electronic device (fig. 19-20) wherein transferring is performed by conductive molecular bonding [0075] (Robin et al., fig. 19-20, [0075]). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to make the simple substitution of the flip-chip bonding transfer of Hwang with the conductive molecular bonding of Robin because molecular boding is well known in the art and such substitution is art recognized equivalence for the same purpose (for mechanical and electrical connection) to obtain predictable results (see MPEP 2144.06).
Claims 6-7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. US PGPub. 2017/0236807 as applied to claims 1 and 4 above, and further in view of Benaissa et al. US PGPub. 2021/0050476. Regarding claim 6, Hwang does not teach the method according to claim 4, wherein an insulating layer in which contact pick-up elements are formed, is interposed between the second substrate (408) and the conductive layer (300). However, Benaissa teaches a method of manufacturing an electronic device (fig. 1-7) wherein an insulating layer (174, fig. 6) [0070] in which contact pick-up elements (173, fig. 6) [0070] are formed, is interposed between the second substrate (170, fig. 6) [0070] and the conductive layer (175, fig. 6) [0071] (Benaissa et al., fig. 6). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the process of Hwang with that of Benaissa because pick-up elements in insulating layers is well known in the art and such structure is art recognized and suitable for the intended purpose of connecting each individual chip to each control circuit (Benaissa et al., [0071]) (see MPEP 2144.07).
Regarding claim 7, Hwang in view of Benaissa teaches the method according to claim 6, further comprising, subsequent to step c), a step of etching the diode stack (120, fig. 4) [0068] so that an elementary diode (160, fig. 5) [0069] is formed vertically in line with each contact pick-up element (173, fig. 6) [0070]) (Benaissa et al., fig. 6). Regarding claim 9, Hwang does not teach the method according to claim 1, further comprising, between steps b) and c), a step of forming hollow vias extending from a face of the first substrate(200) opposite the diode stack (206+208+210) to the diode stack, and passing through the sacrificial layer (204). However, Benaissa teaches a method of manufacturing an electronic device (fig. 1-7) comprising, between steps b) and c), a step of forming hollow vias (fig. 5) [0069] extending from a face of the first substrate (151, fig. 5) [0067] opposite the diode stack (120) to the diode stack (120), and passing through the sacrificial layer (153, fig. 5) [0075](Benaissa et al., fig. 5-6, [0069]) At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the process of Hwang with that of Benaissa because cutting or forming vias in the stack is well known in the art and such structure is art recognized and suitable for the intended purpose singulating the array of LEDs (Benaissa et al., [0069]) (see MPEP 2144.07).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. US PGPub. 2017/0236807 as applied to claim 10 above, and further in view of Pernel et al. US PGPub. 2021/0193873.
Regarding claim 11, Hwang does not teach the method according to claim 10, wherein the sacrificial layer (204) is doped with the first conductivity type (n-type). However, Pernel teaches a method of manufacturing an electronic device (fig. 2A-2D) wherein the sacrificial layer (15, fig. 2B) [0137] is doped with the first conductivity type (n-type, N++ GaN, [0137]) (Pernel et al., fig. 2B, [0137]). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the device of Hwang by using the doping type of the sacrificial layer as taught by Pernel because higher doping of N-type of the sacrificial layer is well known in the art and such process/material is art recognized and suitable for the intended purpose of increasing etch selectivity of the sacrificial layer (Pernel et al., [0126]) (see MPEP 2144.07).
Regarding claim 12, Hwang in view of Pernel teaches the method according to claim 11, wherein the first layer (unintentionally doped 14, 5*1017, fig. 2B) [0108] has a doping level strictly lower, for example at least ten times lower, preferably at least a thousand times lower, than the sacrificial layer (highly doped 15, 1019 or more, fig. 2B) [0125] (Pernel et al., fig. 2B, [0108], [0125]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Schubert et al. US PGPub. 2017/0288087 teaches a method of manufacturing an electronic device comprising electropolishing/electrochemical etching of a sacrificial layer.
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892