22DETAILED ACTION
1. This Office Action is in response to the communications dated 04/17/2025.
Claims 1-25 are pending in this application.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statement (IDS) filed on 12/12/2023, 02/12/2024, and 04/17/2025. The references cited on the PTOL 1449 form have been considered.
Specification
3. The specification has been checked to the extent necessary to determine the presence of possible minor errors. However, the applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1-4, 8-12, and 17- 25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kikuchi et al. (US 2023/0162080)
Regarding claim 1, Kikuchi discloses a package structure, comprising:
a first interposer 30/301 (see Fig. 1E, Fig. 2C) comprising a first alignment feature 405 (and/or the edge/periphery of the interposer; see also para. 0100);
a second interposer 20/201 comprising a second alignment feature 405 and/or 21 (and/or the edge/periphery of the interposer); and
a quantum chip 10/101 bonded to the first interposer 30/301 with an extended portion 103 of the first quantum chip 10/101 extending past a first edge of the first interposer 30/301 (see also para. 0070);
wherein the first interposer 30/301 and the second interposer 20/201 are disposed with the first alignment feature 405 engaging with the second alignment feature 405/21 to cause alignment and coupling of one or more components 11 and/or 102 on the extended portion of the first quantum chip 10/101 with one or more components 21 and/or 202 on the second interposer 20/201.
Regarding claim 2, Kikuchi discloses the package structure of claim 1, wherein:
the first interposer 30/301and the second interposer 20/201 are disposed in a plane; and
the first alignment feature 204 engaging with the second alignment feature 204 causes the alignment in first and second orthogonal directions of the plane. See figs. 1E, 2C.
Regarding claim 3, Kikuchi discloses the package structure of claim 1, wherein:
the first alignment feature comprises the first edge of the first interposer 30/301;
the second alignment feature comprises a second edge of the second interposer 20/201; and
the first alignment feature engaging with the second alignment feature comprises the first edge and the second edge being abutted to cause the alignment and coupling of the one or more components 11/12/102 on the extended portion of the quantum chip 10 with the one or more components 21, 22, 202, 203 on the second interposer 20/201. See figs. 1, 2.
Regarding claim 4, Kikuchi discloses the package structure of claim 1, wherein the first alignment feature (the edge of the first interposer) is fitted within the second alignment feature (the edge of the second interposer) to cause the alignment and coupling of the one or more components on the extended portion of the quantum chip with the one or more components on the second interposer. See figs. 1E, 2C.
Regarding claim 8, Kikuchi discloses a package structure, comprising:
a first interposer 30/301 comprising a first edge (see Fig. 1E, Fig. 2C);
a second interposer 20/201 comprising a second edge; and
a first quantum chip 10/101 bonded to the first interposer 30/301 with an extended portion 103 of the first quantum chip extending past the first edge of the first interposer;
wherein the first interposer 30/301 and the second interposer 20/201 are disposed in a plane with the first edge and the second edge abutted to cause alignment and coupling of one or more components 11/12/102 on the extended portion of the first quantum chip with one or more components 21/22 on the second interposer.
Regarding claim 9, Kikuchi discloses the package structure of claim 8, wherein the first edge and the second edge are abutted to cause the alignment in first and second orthogonal directions of the plane. See figs. 1E, 2C.
Regarding claims 10 and 11, Kikuchi discloses the package structure of claim 8, wherein:
the first interposer comprises a first shape defined at least in part by the first edge;
the second interposer comprises a second shape defined at least in part by the second edge; and
the first shape and the second shape are different shapes, or the first shape and the second shape are the same shape.
It is apparent that these claimed features are inherent or obvious variances from one another since the two shapes would certainly be either different or the same, and these are just simply a change in the shapes of a component, and it would involve only routine skills in the art.
Regarding claim 12, Kikuchi discloses the package structure of claim 8, wherein: the second interposer 20/201 comprises a second quantum chip 50/501 (fig. 2C);
the one or more components 21, 22, 203 on the second interposer 20/201 comprise transmission lines 22, 203 coupled to the second quantum chip 501; and
the one or more components 12 on the extended portion of the first quantum chip comprise one or more quantum bits.
Regarding claim 17, Kikuchi discloses a package structure, comprising:
a first module comprising a first interposer 30/301 (see fig. 2C) which comprises a first edge, and a first quantum chip 10/101 bonded to the first interposer with an extended portion 103 of the first quantum chip extending past the first edge of the first interposer; and
a second module comprising a second interposer 20/201 which comprises a second edge, a second quantum chip 50/201 bonded to the second interposer, and transmission lines 21 & 22 & 203 disposed on the second interposer and coupled to the second quantum chip 501;
wherein the first interposer 30/301 and the second interposer 20/201 are disposed in a plane with the first edge and the second edge abutted to cause alignment and coupling of one or more components 11/12/102 on the extended portion of the first quantum chip with one or more of the transmission lines 21, 22, 203 on the second interposer which are coupled to the second quantum chip.
Regarding claim 18, Kikuchi discloses the package structure of claim 17, wherein the first edge and the second edge are abutted to cause the alignment in first and second orthogonal directions of the plane. See fig. 1E, 2C.
Regarding claim 19, Kikuchi discloses the package structure of claim 17, wherein:
the first interposer comprises a first shape defined at least in part by the first edge;
the second interposer comprises a second shape defined at least in part by the second edge; and
the first shape and the second shape are one of different shapes and the same shape.
It is certainly apparent that the two shapes would be either different or the same. See also the rejection of claims 10-11.
Regarding claim 20, Kikuchi discloses the package structure of claim 17, wherein the first module further comprises a third quantum chip bonded to the first interposer, and transmission lines disposed on the first interposer which couple the first quantum chip and the third quantum chip. See fig. 8.
Regarding claim 21, Kikuchi discloses a method, comprising:
forming interposers 30/301, 20/201 on a substrate 101 (wafer; see para. 0104; see also figs. 1E, 2C); and
cutting the substrate (at scribe region, para. 0104, 0109, 0112) to separate the interposers into at least a first interposer 30/301 comprising a first edge, and a second interposer 20/201 comprising a second edge;
wherein the first edge and the second edge are configured to cause alignment of structures (bottom surface) on the first interposer 30/301 with structures (bottom surface) on the second interposer 20/201 when the first edge and the second edge are abutted with the first interposer and the second interposer disposed in a plane.
Regarding claims 22 and 23, Kikuchi discloses the package structure of claim 8, wherein:
the first interposer comprises a first shape defined at least in part by the first edge;
the second interposer comprises a second shape defined at least in part by the second edge; and
the first shape and the second shape are different shapes, or the first shape and the second shape are the same shape.
Regarding claim 24, Kikuchi discloses a method, comprising:
constructing a first module comprising a first interposer 30/301 (see Fig. 2C) which comprises a first edge, and a first quantum chip 10/101 bonded to the first interposer with an extended portion 103 of the first quantum chip extending past the first edge of the first interposer;
constructing a second module comprising a second interposer 20/201 which comprises a second edge, a second quantum chip 50/501 bonded to the second interposer, and transmission lines 21, 22, 203 disposed on the second interposer and coupled to the second quantum chip 50/501; and
assembling the first module and the second module with the first interposer 30/301 and the second interposer 20/201 are disposed in a plane with the first edge and the second edge abutted to cause alignment and coupling of one or more components 11/12/102 on the extended portion of the first quantum chip 10/101 with one or more of the transmission lines 21/22/203 on the second interposer 20/201 which are coupled to the second quantum chip.
Regarding claim 25, Kikuchi discloses the method of claim 24, wherein: the first interposer comprises a first shape defined at least in part by the first edge;
the second interposer comprises a second shape defined at least in part by the second edge; and
the first shape and the second shape are one of different shapes and the same shape. See figs. 1, 2.
Allowable Subject Matter
6. Claims 5-7, 13-16 are allowable.
Claims 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed package structure (in addition to the other limitations in the claim) comprising:
Claims 5-6:
wherein: the first alignment feature comprises a groove feature;
the second alignment feature comprises a tongue feature, and the second alignment feature is fitted within the first alignment feature to cause the alignment and coupling of the one or more components on the extended portion of the quantum chip with the one or more components on the second interposer.
Claim 7:
wherein: the first alignment feature comprises a first pattern of alignment features;
the second alignment feature comprises a second patten of alignment features; and
the first pattern of alignment features and the second pattern of alignment features are interdigitated to cause the alignment and coupling of the one or more components on the extended portion of the quantum chip with the one or more components on the second interposer.
Claims 13-16:
Wherein the package structure further comprising a third interposer comprising a third edge, wherein:
the third interposer is disposed on the plane with the first interposer and the second interposer; and
the second edge of the first interposer and the third edge of the third interposer are abutted to cause alignment and coupling of one or more components on the second extended portion of the first quantum chip with one or more components on the third interposer.
Conclusion
7. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 February 12, 2026