Prosecution Insights
Last updated: August 17, 2026
Application No. 18/537,536

SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Dec 12, 2023
Priority
Mar 14, 2023 — RE 10-2023-0033390
Examiner
GHYKA, ALEXANDER G
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
1095 granted / 1306 resolved
+15.8% vs TC avg
Moderate +14% lift
Without
With
+13.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
43 currently pending
Career history
1331
Total Applications
across all art units

Statute-Specific Performance

§101
1.6%
-38.4% vs TC avg
§103
56.2%
+16.2% vs TC avg
§102
15.4%
-24.6% vs TC avg
§112
12.7%
-27.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1306 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of Specie A (Claims 1-11) in the reply filed on 2/16/26 is acknowledged. The traversal is on the ground(s) that the Species share common core elements and a search and examination may be made without serious burden. This is not found persuasive because even though the Species share common elements, the Species also contain mutually exclusive elements which require a serious burden for search and examination purposes. Rejoinder issues will be addressed upon indication of allowable subject matter. The requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-11 are rejected under 35 U.S.C. 103 as being obvious over Kim et al (US 2022/0293600). The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02. With respect to Claim 1, Kim et al discloses a semiconductor device (Figures 27A-27B) , comprising a substrate (100) including an active pattern (AP1); a channel pattern (CH1) on the active pattern, the channel pattern including a plurality of semiconductor patterns (SP1, Sp2 and SP3) that are vertically stacked and spaced apart from each other; a source/drain pattern (SD1) connected to the plurality of semiconductor patterns; a gate electrode (GE) on the plurality of semiconductor patterns, the gate electrode including a plurality of inner electrodes (three lower GE) between neighboring ones of the plurality of semiconductor patterns and an outer electrode (top GE)on the uppermost semiconductor pattern; and a capping pattern (Figure 6A-6B and Figures 27A-27B, GP) on a top surface of the outer electrode, wherein a line – width of the outer electrode is a first width, wherein the outer electrode has a first height (Figures 6A-6B and 27A-27B). Kim et al discloses varying the dimensions in Figures 6A-6B and corresponding text. See Figures 6A-6B and 27A-27B, and corresponding text, especially paragraphs 42-56, 96-107 and 153-161. However, Kim et al does not explicitly disclose wherein the first height is equal to or less than the first width. It would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to arrive at the claimed height/width dimensions as changes in shape are prima facie obvious in the absence of unobvious results. See In re Dailey, 149 USPQ 47 (CCPA 1966). Moreover, changes in size are prima facie obvious in the absence of unobvious results. See In re Rose, 105 USPQ 237 (CCPA 1955). Adjusting the dimensions of the electrode in order to optimize the performance of the device would be within the skill of one of ordinary skill in the art in view of In re Dailey and In re Rose, supra. With respect to Claim 2 and the range of the width, changes in size are prima facie obvious in the absence of unobvious results. See In re Rose, 105 USPQ 237 (CCPA 1955). With respect to Claim 3 and the range of the height, changes in size are prima facie obvious in the absence of unobvious results. See In re Rose, 105 USPQ 237 (CCPA 1955). With respect to Claim 4, and the limitation “ wherein the capping pattern includes a material having an etch selectivity with respect to silicon oxide”, Kim et al discloses the claimed materials. See paragraph 56. With respect to Claim 5, Kim et al discloses the claimed capping pattern materials. See paragraph 56. With respect to Claim 6, Kim et al discloses an active contact (AC) electrically connected to the source/drain pattern (SD1), wherein a top surface of the active contact is at a same level as a top surface of the capping pattern. See Figures 27A-27B and corresponding text. With respect to Claim 7, Kim et al discloses a gate dielectric layer (GI) on a lateral surface and a bottom surface of the outer electrode (top GE) ; and a gate spacer (GS) on the lateral surface of the outer electrode, wherein the capping pattern (GT) covers the top surface of the outer electrode, a top surface of the gate dielectric layer, and a top surface of the gate spacer. See Figures 27A-27B and corresponding text. With respect to Claim 8, and the limitation “ the outer electrode, the gate dielectric, and the gate spacer constitute a gate structure, and a width in a first direction is the same as a width in the first direction of the capping pattern”, it would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to arrive at the claimed dimensions as changes in shape are prima facie obvious in the absence of unobvious results. See In re Dailey, 149 USPQ 47 (CCPA 1966). Moreover, changes in size are prima facie obvious in the absence of unobvious results. See In re Rose, 105 USPQ 237 (CCPA 1955). Adjusting the dimensions of the gate structures in order to optimize the performance of the device would be within the skill of one of ordinary skill in the art in view of In re Dailey and In re Rose, supra. With respect to Claim 9, and the limitation “wherein the outer electrode, the gate dielectric layer, and the gate spacer constitute a gate structure, and a width in a first direction of the gate structure is different from a width in the first direction of the capping pattern”, it would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to arrive at the claimed dimensions as changes in shape are prima facie obvious in the absence of unobvious results. See In re Dailey, 149 USPQ 47 (CCPA 1966). Moreover, changes in size are prima facie obvious in the absence of unobvious results. See In re Rose, 105 USPQ 237 (CCPA 1955). Adjusting the dimensions of the gate structure in order to optimize the performance of the device would be within the skill of one of ordinary skill in the art in view of In re Dailey and In re Rose, supra. With respect to Claim 10, Kim et al discloses further comprising an active contact (AC) electrically connected to the source/drain pattern (SD1). See Figures 27A-27B and corresponding text. Moreover, with respect to the limitation “wherein a width in the first direction of the active contact is less than a width in the first direction of the source/drain pattern”, the limitation is disclosed in Figures 27A-27B, as the active contact narrows in the lower part. With respect to Claim 11, Kim et al discloses further comprising an active contact (AC) electrically connected to the source/drain pattern (SD1), wherein the active contact includes, body part extending to the top surface of the gate spacer, and a protrusion part protruding from the body part to the source/ drain pattern, the limitation is disclosed in Figures 27A-27B, as the active contact narrows in the lower part. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER G GHYKA whose telephone number is (571)272-1669. The examiner can normally be reached Monday-Friday 9-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at 571 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. AGG May 13, 2025 /ALEXANDER G GHYKA/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Dec 12, 2023
Application Filed
May 15, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
98%
With Interview (+13.7%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1306 resolved cases by this examiner. Grant probability derived from career allowance rate.

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