DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification/Claim Objections
Claims 11-20 and the disclosure are objected to because of the following informalities:
“Tab cell” is used in Claims 11, 16, and throughout the Specification to refer to a cell which provides voltage to power interconnection lines. The term used in the art is “tap cell”, see e.g. U.S. PGPub 2024/0194601, [0041]; U.S. PGPub 2020/0373241, [0004]).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 4 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 1, from which claim 4 depends, requires that the density and resistivity of the first metal pattern are greater than the density and resistivity of the second metal pattern.
Claim 4 specifies that the first and second metal pattern include different metals, the first metal pattern includes at least one selected from a group consisting of silver (Ag), gold (Au), platinum (Pt), copper (Cu), iridium (Ir), ruthenium (Ru), scandium (Sc), yttrium (Y), and lanthanum (La), and the second metal pattern includes at least one selected from a group consisting of tungsten (W), molybdenum (Mo), ruthenium (Ru), aluminum (Al), titanium (Ti), and tantalum (Ta).
Resistivity (10-8 mohm)1
First group of metals
Second group of metals
Density (g/cm3)2
First group of metals
Second group of metals
Lanthanum 6.1
Iridium 22.42
Yttrium 5.7
Platinum 21.45
Scandium 5.5
Gold 19.3
Titanium 4
Tungsten 19.25
Tantalum 1.3
Tantalum 16.65
Platinum 1.1
Ruthenium 12.37
Ruthenium 12.37
Ruthenium 7
Ruthenium 7
Silver 10.49
Molybdenum 5
Molybdenum 10.28
Tungsten 5
Copper 8.96
Iridium 4.7
Lanthanum 6.15
Aluminum 2.6
Titanium 4.5
Gold 2.2
Yttrium 4.47
Copper 1.7
Scandium 2.99
Silver 1.6
Aluminum 2.7
Several metals cannot satisfy both claim requirements: Gold, copper, and silver do not have a higher resistivity than any of the metals from the second group and no metal from the first group has a higher resistivity and density than tantalum. For these metals to satisfy the claim, the patterns must comprise alloys. No specific combinations of metals from the two groups that satisfy both of the claim requirements are disclosed. 53 unique combinations of metals are possible just from the single elements, only some of which satisfy the claim requirements, but the possibilities become vast once alloys are considered. A person of ordinary skill cannot practice the invention as claimed without investigating thousands of possibilities with no guidance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 5-6, 8, 10-11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (U.S. PGPub 2023/0069137) in view of Park (U.S. PGPub 2021/0020544).
Regarding claim 1, Tsai teaches a semiconductor device (Figs. 1-2E) comprising:
an active pattern on a substrate (Fig. 1, CFETs 150a-f comprise nanosheets depicted but not labeled, [0039], [0051]),
a source/drain pattern on the active pattern (Figs. 1, 2D, [0051], epi, depicted around nanosheets but not labeled),
a first metal layer on the source/drain pattern, the first metal layer comprising a power interconnection line (Figs. 2A-2B, 120a-c, [0041]),
a through-via electrically connected to the power interconnection line, the through-via vertically extending to penetrate the substrate ([0043], Fig. 2D, 165, [0048]; [0043], Fig. 3D, 360a, feed-through via),
a power delivery network layer on a bottom surface of the substrate (BM1, Fig. 2A, [0044], backside),
and a lower through-via between the power delivery network layer and the through-via (BV, Fig. 2D, [0048]).
Tsai does not explicitly teach wherein the through-via comprises a first metal pattern connected to the lower through-via, a second metal pattern stacked on the first metal pattern, wherein a density of the first metal pattern is greater than a density of the second metal pattern, and wherein a resistivity of the first metal pattern is greater than a resistivity of the second metal pattern.
Park teaches a through-via comprising a first metal pattern connected to a lower via and a second metal pattern on the first metal pattern (Figs. 1-5, 161/162; Fig. 3, [0045]), wherein a density and resistivity of the first metal pattern are different from the second metal pattern ([0032]). This teaches four possibilities: 1) both density and resistivity of the first metal pattern are higher, 2) only density of the first metal pattern is higher, 3) only resistivity of the first metal pattern is higher, and 4) both density and resistivity of the first metal pattern are lower. One out of the four options corresponds to the claim limitation, where a density and resistivity of the first metal pattern are different from the second metal pattern. A person of ordinary skill has reason to try the known options available. See MPEP 2143(I)E.
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Park with Tsai such that the through-via comprises a first metal pattern connected to the lower through-via, a second metal pattern stacked on the first metal pattern, wherein a density of the first metal pattern is greater than a density of the second metal pattern, and wherein a resistivity of the first metal pattern is greater than a resistivity of the second metal pattern for the purpose of filling the via without voids (Park, [0004]).
Regarding claim 2, the combination of Tsai and Park teaches wherein an end portion of the first metal pattern is lower than the bottom surface of the substrate (Park, [0020]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Tsai and Park because the prior art teaches every element, a person of ordinary skill could have combined them as claimed and in combination each element performs the same function as it does separately, and the combination would have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143(I)A.
Regarding claim 5, the combination of Tsai and Park teaches wherein a volume of the second metal pattern is greater than a volume of the first metal pattern in the through-via (Park, Figs. 1-5, either conductive layer may have the greater volume). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Tsai and Park because the prior art teaches every element, a person of ordinary skill could have combined them as claimed and in combination each element performs the same function as it does separately, and the combination would have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143(I)A.
Regarding claim 6, the combination of Tsai and Park teaches wherein the source/drain pattern includes a pair of source/drain patterns adjacent to each other, and the through-via penetrates an interlayer insulating layer between the pair of source/drain patterns (Lee, Fig. 1, an ILD is necessarily present between elements). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Tsai and Park for the reasons set forth in the rejection of claim 1.
Regarding claim 8, the combination of Tsai and Park teaches wherein the first metal pattern includes a vertical extension portion at a side thereof, the first metal pattern has a concave top surface due to the vertical extension portion, and the second metal pattern has a convex bottom surface being in contact with the concave top surface of the first metal pattern (Figs. 4-5). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Tsai and Park for the reasons set forth in the rejection of claim 1.
Regarding claim 10, the combination of Tsai and Park teaches wherein the power delivery network layer is configured to apply a source voltage or a drain voltage to the power interconnection line (Tsai, [0040]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Tsai and Park for the reasons set forth in the rejection of claim 1.
Regarding claim 11, Tsai teaches a semiconductor device comprising:
a plurality of power interconnection lines on a substrate, the power interconnection lines arranged in a first direction, and the power interconnection lines extending in a second direction in parallel to each other (Fig. 2A, 120, [0040], first direction Y, second direction X);
a plurality of logic cells two-dimensionally arranged on the substrate ([0035], power is provided to standard (logic) cells)
a plurality of tab cells arranged in the first direction on the substrate (Fig. 2B), and
a power delivery network layer under the substrate (BM1, Fig. 2A, [0044], backside),
wherein the plurality of tab cells comprises,
a plurality of through-vias electrically connected to the plurality of power interconnection lines, respectively, ([0043], Fig. 2D, 165, [0048]; [0043], Fig. 3D, 360a, feed-through via),
a plurality of lower through-vias electrically connecting the plurality of through-vias to the power delivery network layer, respectively (BV, Fig. 2D, [0048]),
wherein the power delivery network layer is configured to apply voltages to the plurality of power interconnection lines through the through-vias and the lower through-vias ([0041]-[0042]).
Tsai does not explicitly teach wherein the through-vias each comprise a first metal pattern connected to a corresponding lower through-via, a second metal pattern stacked on the first metal pattern, wherein a resistivity of the first metal pattern is greater than a resistivity of the second metal pattern.
Park teaches a through-via comprising a first metal pattern connected to a lower via and a second metal pattern on the first metal pattern (Figs. 1-5, 161/162; Fig. 3, [0045]), wherein a resistivity of the first metal pattern is different from the second metal pattern ([0032]). If the resistivity is different it must be either greater or lower. A person of ordinary skill has reason to try the known options available. See MPEP 2143(I)E.
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Park with Tsai such that the through-vias each comprise a first metal pattern connected to a corresponding lower through-via, a second metal pattern stacked on the first metal pattern, wherein a resistivity of the first metal pattern is greater than a resistivity of the second metal pattern for the purpose of filling the via without voids (Park, [0004]).
Regarding claim 13, the combination of Tsai and Park teaches wherein a volume of the second metal pattern is greater than a volume of the first metal pattern in a corresponding through-via (Park, Figs. 1-5, either conductive layer may have the greater volume). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Tsai and Park because the prior art teaches every element, a person of ordinary skill could have combined them as claimed and in combination each element performs the same function as it does separately, and the combination would have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143(I)A.
Claims 3 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (U.S. PGPub 2023/0069137) in view of Park (U.S. PGPub 2021/0020544) and Xie (U.S. PGPub 2023/0402318).
Regarding claim 3, the combination of Tsai and Park does not explicitly teach wherein the lower through-via surrounds the end portion of the first metal pattern.
Xie teaches a backside power delivery network layer (140, [0075]), a lower through-via (142, [0076]), and a through-via connected to the lower through-via (126, [0078]), wherein the lower through-via surrounds the end portion of the through-via (Fig. 25, [0087]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Xie with Tsai and Park such that the lower through-via surrounds the end portion of the first metal pattern for the purpose of lowering resistance (Xie, [0079]-[0080]).
Regarding claim 7, the combination of Tsai and Park does not explicitly teach wherein a width of the through-via becomes progressively less toward the power delivery network layer, and a width of the lower through-via becomes progressively greater toward the power delivery network layer.
Xie teaches a backside power delivery network layer (140, [0075]), a lower through-via (142, [0076]), and a through-via connected to the lower through-via (126, [0078]), wherein a width of the through-via becomes progressively less toward the power delivery network layer, and a width of the lower through-via becomes progressively greater toward the power delivery network layer (Fig. 22, [0081]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Xie with Tsai and Park such that a width of the through-via becomes progressively less toward the power delivery network layer, and a width of the lower through-via becomes progressively greater toward the power delivery network layer for the purpose of lowering resistance (Xie, [0079]-[0080]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai (U.S. PGPub 2023/0069137) in view of Park (U.S. PGPub 2021/0020544) and Lanzillo (U.S. PGPub 2022/0199521).
Regarding claim 4, the combination of Tsai and Park teaches wherein the first metal pattern and the second metal pattern include different metals and wherein one metal may include copper (Park, [0031]) but does not explicitly teach wherein the first metal pattern includes at least one selected from a group consisting of silver (Ag), gold (Au), platinum (Pt), copper (Cu), iridium (Ir), ruthenium (Ru), scandium (Sc), yttrium (Y), and lanthanum (La), and the second metal pattern includes at least one selected from a group consisting of tungsten (W), molybdenum (Mo), ruthenium (Ru), aluminum (Al), titanium (Ti), and tantalum (Ta).
Lanzillo teaches a through-via comprising a first metal pattern connected to a lower via and a second metal pattern on the first metal pattern (Fig. 1, via 138, 134/136, [0027]), wherein the first and second metal pattern include at least one metal selected from a group comprising ruthenium, molybdenum, tungsten, platinum, and iridium ([0035]) and wherein the materials are chosen based on etching properties, cost, and electric resistivity ([0035]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Lanzillo with Tsai and Park such that the first metal pattern includes at least one selected from a group consisting of silver (Ag), gold (Au), platinum (Pt), copper (Cu), iridium (Ir), ruthenium (Ru), scandium (Sc), yttrium (Y), and lanthanum (La), and the second metal pattern includes at least one selected from a group consisting of tungsten (W), molybdenum (Mo), ruthenium (Ru), aluminum (Al), titanium (Ti), and tantalum (Ta) for the purpose of choosing appropriate metals for each pattern based on the etching properties, cost, and electric resistivity (Lanzillo, [0035]; Park, [0032]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai (U.S. PGPub 2023/0069137) in view of Park (U.S. PGPub 2021/0020544) and Kang (U.S. PGPub 2024/0087957).
Regarding claim 12, the combination of Tsai and Park does not explicitly teach wherein an end portion of the first metal pattern is lower than a bottom surface of the substrate, and a corresponding one of the lower through-vias is in contact with the end portion.
Kang teaches a power delivery network layer, a lower through-via connected to the power delivery network layer, and a through-via connected to the lower through via, wherein an end portion of the first metal pattern is lower than a bottom surface of the substrate, and a corresponding one of the lower through-vias is in contact with the end portion (power delivery network layer BSPDN, lower through via BPR, through-via VBPR, substrate 2002, [0077]-[0084]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kang with Tsai and Park such that an end portion of the first metal pattern is lower than a bottom surface of the substrate, and a corresponding one of the lower through-vias is in contact with the end portion for the purpose of reducing contact resistance (Kang, [0077]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai (U.S. PGPub 2023/0069137) in view of Park (U.S. PGPub 2021/0020544) and Yu (U.S. PGPub 2019/0027402).
Regarding claim 14, the combination of Tsai and Park does not explicitly teach wherein an etch resistance of the first metal pattern to dilute hydrofluoric acid (DHF) or diluted sulfate peroxide (DSP) is greater than an etch resistance of the second metal pattern to the DHF or the DSP.
Yu teaches wherein an etch resistance of a lower metal in an interconnect to a cleaning solution is greater than an etch resistance of an upper metal in an interconnect to the cleaning solution (Figs. 2H-2I, [0034]), where the cleaning solution may be diluted sulfate peroxide ([0034], combination of sulfuric acid and hydrogen peroxide diluted in water).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Yu with Tsai and Park such that an etch resistance of the first metal pattern to dilute hydrofluoric acid (DHF) or diluted sulfate peroxide (DSP) is greater than an etch resistance of the second metal pattern to the DHF or the DSP for the purpose of preventing the creation of voids during cleaning (Yu, [0003]).
Claims 16, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (U.S. PGPub 2023/0069137) in view of Kang 2021 (U.S. PGPub 2021/0358902) and Park (U.S. PGPub 2021/0020544).
Regarding claim 16, Tsai teaches a semiconductor device comprising:
a first power interconnection line and a second power interconnection line on a substrate, the first and second power interconnection lines spaced apart from each other in a first direction, and the first and second power interconnection lines extending in a second direction in parallel to each other (Fig. 2A, 120, [0040], first direction Y, second direction X);
a logic cell and a tab cell between the first and second power interconnection lines, the logic cell and the tab cell adjacent to each other in the second direction ([0035], power is provided to standard (logic) cells; Figs. 2B-2C, [0047]),
a first through-via and a second through-via on the tab cell, the first and second through-vias electrically connected to the first and second power interconnection lines, respectively ([0043], Fig. 2D, 165, [0048]; [0043], Fig. 3D, 360a, feed-through via),
a power delivery network layer on a bottom surface of the substrate (BM1, Fig. 2A, [0044], backside), and
a first lower through-via and a second lower through-via between the power delivery network layer and the first and second through-vias, respectively (BV, Fig. 2D, [0048]).
Tsai does not explicitly teach:
a first active pattern and a second active pattern on the logic cell, the first and second active patterns spaced apart from each other in the first direction;
a first channel pattern and a first source/drain pattern on the first active pattern;
a second channel pattern and a second source/drain pattern on the second active pattern, the second source/drain pattern having a conductivity type different from that of the first source/drain pattern;
a gate electrode on the first and second channel patterns;
a gate insulating layer between the gate electrode and the first and second channel patterns;
a gate spacer on a sidewall of the gate electrode;
a gate capping pattern on a top surface of the gate electrode;
an interlayer insulating layer covering the first and second source/drain patterns and the gate capping pattern;
an active contact penetrating the interlayer insulating layer and electrically connected to at least one of the first and second source/drain patterns;
a metal-semiconductor compound layer between the active contact and the at least one of the first and second source/drain patterns;
a gate contact penetrating the interlayer insulating layer and the gate capping pattern and electrically connected to the gate electrode.
Kang 2021 teaches a semiconductor device comprising first and second power interconnection lines spaced apart in a first direction and extending in a second direction in parallel (Fig. 1, PR, [0024], first direction Y, second direction X),
logic and tab cells between power interconnection lines ([0028]),
a first active pattern and a second active pattern on the logic cell, the first and second active patterns spaced apart from each other in the first direction (Figs. 6-7, F1/F2, [0033]),
a first channel pattern and a first source/drain pattern on the first active pattern, a second channel pattern and a second source/drain pattern on the second active pattern, the second source/drain pattern having a conductivity type different from that of the first source/drain pattern (Fig. 7A, SD1/SD2, NW1/NW2, [0069]-[0071]),
a gate electrode on the first and second channel patterns, a gate insulating layer between the gate electrode and the first and second channel patterns (Fig. 7B, GL/GI, [0072]),
an interlayer insulating layer covering the first and second source/drain patterns, an active contact penetrating the interlayer insulating layer and electrically connected to at least one of the first and second source/drain patterns, a metal-semiconductor compound layer between the active contact and the at least one of the first and second source/drain patterns, a gate contact penetrating the interlayer insulating layer and the gate capping pattern and electrically connected to the gate electrode ([0015], BEOL processing including forming a dielectric, silicidation, forming vias).
The Examiner takes official notice that forming gate spacers and a gate capping layer is a standard part of forming a transistor.
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kang 2021 with Tsai such that the device comprises a first active pattern and a second active pattern on the logic cell, the first and second active patterns spaced apart from each other in the first direction, a first channel pattern and a first source/drain pattern on the first active pattern, a second channel pattern and a second source/drain pattern on the second active pattern, the second source/drain pattern having a conductivity type different from that of the first source/drain pattern, a gate electrode on the first and second channel patterns, a gate insulating layer between the gate electrode and the first and second channel patterns, a gate spacer on a sidewall of the gate electrode, a gate capping pattern on a top surface of the gate electrode, an interlayer insulating layer covering the first and second source/drain patterns and the gate capping pattern, an active contact penetrating the interlayer insulating layer and electrically connected to at least one of the first and second source/drain patterns, a metal-semiconductor compound layer between the active contact and the at least one of the first and second source/drain patterns, a gate contact penetrating the interlayer insulating layer and the gate capping pattern and electrically connected to the gate electrode for the purpose of forming the logic cell (Kang 2021, [0023], Tsai, [0035]).
Tsai further does not explicitly teach wherein each of the first and second through-vias comprises, a first metal pattern being in contact with a corresponding one of the first and second lower through-vias, and a second metal pattern stacked on the first metal pattern, and wherein the first metal pattern and the second metal pattern include different metals.
Park teaches a through-via comprising a first metal pattern connected to a lower via and a second metal pattern on the first metal pattern (Figs. 1-5, 161/162; Fig. 3, [0045]), wherein the first metal pattern and the second metal pattern include different metals ([0031]-[0032]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Park with Tsai and Kang 2021 such that each of the first and second through-vias comprises, a first metal pattern being in contact with a corresponding one of the first and second lower through-vias, and a second metal pattern stacked on the first metal pattern, and wherein the first metal pattern and the second metal pattern include different metals for the purpose of filling the via without voids (Park, [0004]).
Regarding claim 18, the combination of Tsai, Kang 2021, and Park teaches wherein each of the first and second channel patterns comprises a plurality of semiconductor patterns stacked sequentially and spaced apart from each other (Tsai, Fig. 2D; Kang 2021, Fig. 7B). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Tsai, Kang 2021, and Park for the reasons set forth in the rejection of claim 16.
Regarding claim 20, the combination of Tsai, Kang 2021, and Park teaches interconnection lines on the logic cell, wherein the interconnection lines are electrically connected to the active contact and the gate contact, respectively (Kang 2021, [0115], BEOL processing), and wherein the interconnection lines are at a same level as the first and second power interconnection lines (Tsai, [0035], delivering power from the front side; [0099], metal layer M0 provides power). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Tsai, Kang 2021, and Park for the reasons set forth in the rejection of claim 16.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai (U.S. PGPub 2023/0069137) in view of Kang 2021 (U.S. PGPub 2021/0358902), Park (U.S. PGPub 2021/0020544), and Xie (U.S. PGPub 2023/0402318).
Regarding claim 17, the combination of Tsai, Kang 2021, and Park does not explicitly teach wherein a width of each of the first and second through-vias becomes progressively less toward the power delivery network layer, and a width of each of the first and second lower through-vias becomes progressively greater toward the power delivery network layer.
Xie teaches a backside power delivery network layer (140, [0075]), a lower through-via (142, [0076]), and a through-via connected to the lower through-via (126, [0078]), wherein a width of the through-via becomes progressively less toward the power delivery network layer, and a width of the lower through-via becomes progressively greater toward the power delivery network layer (Fig. 22, [0081]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Xie with Tsai and Park such that a width of each of the first and second through-vias becomes progressively less toward the power delivery network layer, and a width of each of the first and second lower through-vias becomes progressively greater toward the power delivery network layer. for the purpose of lowering resistance (Xie, [0079]-[0080]).
Allowable Subject Matter
Claims 9, 15, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Regarding dependent claims 9, 15, and 19, the prior art, alone or in combination, does not teach a spacer on a sidewall of the through-via, wherein an uppermost portion of the first metal pattern is lower than a top surface of the second metal pattern, and wherein at least a portion of the second metal pattern is in direct contact with the spacer, in combination with the other respective limitations of each claim.
Lanzillo (U.S. PGPub 2023/0402381) teaches a through-via connecting a backside power rail to an upper interconnection layer, where a spacer is on a partial sidewall of the through-via (Fig. 2, 10, 24, 22, 18L, [0029]), but the spacer is surrounding the upper portion of the through-via and no teachings regarding two metals are present.
Conclusion
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/ALIA SABUR/ Primary Examiner, Art Unit 2812
1 https://periodictable.com/Properties/A/Resistivity.v.log.html
2 https://periodictable.com/Properties/A/Density.v.html
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