DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 20 is objected to because of the following informalities: there is punctuation error in line 8 wherein line 8 ends by “, ;”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-9, 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2018/0166449 A1 hereinafter referred to as “Park”).
With respect to claim 1, Park discloses, in Figs.1-17, a semiconductor device, comprising: a plurality of device isolation layers (105) extending in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a plurality of active regions (103) between the plurality of device isolation layers (105) and spaced apart from each other in the first horizontal direction (see Par.[0027]-[0028] wherein the unit active region 103 may be defined by forming the element isolation region 105 in the substrate (100 in FIG. 3); the element isolation region 105 may include silicon oxide or a silicon oxide-based insulating material); a plurality of insulating structures (120) between the plurality of active regions (103) (see Par.[0039] wherein the gate insulating layer 120 may be formed along sidewalls and a bottom surface of the first trench 110 formed in the substrate 100; the gate insulating layer 120 may include, for example, a high-dielectric constant (high-k) dielectric having a dielectric constant higher than that of silicon oxide or silicon nitride, for example, having a dielectric constant of about 10 to about 25; for example, the high-k dielectric may include at least one of hafnium oxide, lanthanum oxide, zirconium oxide, tantalum oxide, titanium oxide, yttrium oxide, aluminum oxide, and combinations thereof); and a gate structure (130) extending in a third horizontal direction between the first horizontal direction and the second horizontal direction and intersecting the plurality of active regions (see Par.[0038] wherein the gates of the transistors may be connected to the word lines 130), wherein two adjacent side surfaces of each of the plurality of active regions (103) define an acute angle (see Fig.2 wherein two adjacent surfaces of active regions are in DR1 and DR3 directions respectively forming an acute angle ꝋ2), and wherein at least a portion of at least one of the plurality of insulating structures (120) is between a corresponding pair of the plurality of active regions (103) and between a corresponding pair of the plurality of device isolation layers (105) and overlaps the corresponding pair of the plurality of active regions (103) in the first horizontal direction (see Figs.2-3 for insulating 120 between and overlapping active regions 103).
With respect to claim 3, Park discloses, in Figs.1-17, the semiconductor device, wherein the plurality of active regions (103) includes first side surfaces and second side surfaces spaced apart from each other in the first horizontal direction, and wherein the first side surfaces and the second side surfaces are inwardly curved surfaces (see Fig.2).
With respect to claim 4, Park discloses, in Figs.1-17, the semiconductor device, wherein, in a plan view, the plurality of insulating structures (12, 160) have a circular shape (see Fig.2, wherein plug 160 and underneath liner 120 are circular shape).
With respect to claim 5, Park discloses, in Figs.1-17, the semiconductor device, wherein a portion of at least one of the plurality of insulating structures (120) overlaps one or more of the plurality of device isolation layers (105) in the first horizontal direction (see Fig.2).
With respect to claim 6, Park discloses, in Figs.1-17, the semiconductor device, wherein maximum horizontal width of the plurality of insulating structure (120) are greater than horizontal widths of the plurality of active regions (103) in the second horizontal direction (see Fig.2).
With respect to claim 7, Park discloses, in Figs.1-17, the semiconductor device, wherein the plurality of insulating structures (120) are configured as a single layer (see Fig.3).
With respect to claim 8, Park discloses, in Figs.1-17, the semiconductor device, wherein the first horizontal direction is a major axis-direction of the plurality of active regions (103), and wherein the second horizontal direction is a minor axis-direction of the plurality of active regions (103) (see Fig.2).
With respect to claim 9, Park discloses, in Figs.1-17, the semiconductor device, wherein the plurality of device isolation layers (105) include a plurality of first device isolation layers (105) and a plurality of second device isolation layers (105) alternating in the second horizontal direction (see Fig.2).
With respect to claim 20, Park discloses, in Figs.1-17, a semiconductor device, comprising: a first active region (103) and a second active region (103) extending in a first horizontal direction and spaced apart from each other in the first horizontal direction; a first device isolation layer (105) and a second device isolation layer (105) spaced apart from each other in a second horizontal direction intersecting the first horizontal direction, the first device isolation layer and the second device isolation layer extending in the first horizontal direction, the first active region and the second active region interposed between the first device isolation layer and the second device isolation layer (see Par.[0038] wherein the two transistors may include a first source/drain region 107a formed in the unit active region 103 between the two word lines 130, and a second source/drain region 107b formed between each word line 130 and the element isolation region 105); an insulating structure (120) between the first active region and the second active region and in contact with the first active region and the second active region (see Par.[0039] wherein the two transistors may include a first source/drain region 107a formed in the unit active region 103 between the two word lines 130, and a second source/drain region 107b formed between each word line 130 and the element isolation region 105); a gate structure (130) extending in a third horizontal direction between the first horizontal direction and the second horizontal direction and intersecting the first active region (see Par.[0040]-[0041] wherein the word line 130 may be in a recessed form. The word line 130 may be formed of, for example, doped polysilicon, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium (Ti), tantalum (Ta), tungsten (W) or the like, but the present disclosure is not limited thereto); and a bitline structure (170) intersecting the first active region and extending in a fourth horizontal direction orthogonal to the third horizontal direction, wherein a side surface of the first active region in contact with the insulating structure (120) is a curved surface recessed toward a central portion of the first active region, and wherein at least a portion of the insulating structure is between the first active region and the second active region and between the first device isolation layer and the second device isolation layer, and overlaps the first active region in the first horizontal direction (see Par.[0044] wherein the bit line 170 may be formed to be on and electrically connected to the first contact plug 160; see Fig.2 for curved active region surfaces).
Claims 1, 3-5, 7, 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US 2014/0117566 A1 hereinafter referred to as “Choi”).
With respect to claim 1, Choi discloses, in Figs.1-24, a semiconductor device, comprising: a plurality of device isolation layers (63) extending in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a plurality of active regions (45) between the plurality of device isolation layers (63) and spaced apart from each other in the first horizontal direction; a plurality of insulating structures (65) between the plurality of active regions (45); and a gate structure (67) extending in a third horizontal direction between the first horizontal direction and the second horizontal direction and intersecting the plurality of active regions (45) (see Par.[0041] wherein referring to FIGS. 1 and 2, a plurality of parallel-trenches 41 and intersect-trenches 49 by which a plurality of active regions 45 are confined may be formed in the semiconductor substrate 21; a device isolation layer 63 filling the parallel-trenches 41 and the intersect-trenches 49 may be formed; a plurality of word lines 67 intersecting the active regions 45 and the device isolation layer 63 may be formed; a gate dielectric layer 65 may be formed between the word lines 67 and the active regions 45), wherein two adjacent side surfaces (S1-S2 and S3-S4) of each of the plurality of active regions (45) define an acute angle (see Par.[0046]-[0049] wherein as illustrated in FIG. 3, the first acute angle .theta.1 may be interpreted as a crossing angle between the second side surface S2 and the bit line 75, and the second acute angle .theta.2 may be interpreted as a crossing angle between the second side surface S2 and the third side surface S3; the first end 45E1 may protrude away from the bit line 75; the second end 45E2 may protrude away from the bit line 75; each of the first end 45E1 and the second end 45E2 may be connected corresponding one of the buried contact plugs (reference number 83 of FIG. 1)), and wherein at least a portion of at least one of the plurality of insulating structures (65) is between a corresponding pair of the plurality of active regions (45) and between a corresponding pair of the plurality of device isolation layers (63) and overlaps the corresponding pair of the plurality of active regions (45) in the first horizontal direction (see Figs.1-2, for insulating 65 between and overlapping active regions 45).
With respect to claim 3, Choi discloses, in Figs.1-24, the semiconductor device, wherein the plurality of active regions (45) includes first side surfaces and second side surfaces spaced apart from each other in the first horizontal direction, and wherein the first side surfaces and the second side surfaces are inwardly curved surfaces (see Fig.2).
With respect to claim 4, Choi discloses, in Figs.1-24, the semiconductor device, wherein, in a plan view, the plurality of insulating structures (65) have a circular shape (see Figs.2-3 wherein insulating directly aligned with circular storage elements are circular).
With respect to claim 5, Choi discloses, in Figs.1-24, the semiconductor device, wherein a portion of at least one of the plurality of insulating structures (65) overlaps one or more of the plurality of device isolation layers (63) in the first horizontal direction (see Figs.2-3).
With respect to claim 7, Choi discloses, in Figs.1-24, the semiconductor device, wherein the plurality of insulating structures (65) are configured as a single layer (see Fig.2).
With respect to claim 9, Choi discloses, in Figs.1-24, the semiconductor device, wherein the plurality of device isolation layers (63) include a plurality of first device isolation layers (63) and a plurality of second device isolation layers (63) alternating in the second horizontal direction (see Figs.1-2).
Claims 1-9, 15, 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by An et al. (US 2022/0181326 A1 hereinafter referred to as “An”).
With respect to claim 1, An discloses, in Figs.1A-18D, a semiconductor device, comprising: a plurality of device isolation layers (IL, ST_TR1) extending in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a plurality of active regions (ACT) between the plurality of device isolation layers (IL, ST_TR1) and spaced apart from each other in the first horizontal direction; a plurality of insulating structures (ST_TR2) between the plurality of active regions (ACT) (see Par.[0023]-[0024] wherein the device isolation layer ST may fill the first and second trenches TR1 and TR2 between the active patterns ACT); and a gate structure (GE) extending in a third horizontal direction between the first horizontal direction and the second horizontal direction and intersecting the plurality of active regions (see Par.[0028]-[0029] wherein gate electrodes GE may be provided to run (i.e., extend) across the active patterns ACT and the device isolation layer ST; the gate electrodes GE may be provided in corresponding third trenches TR3, as illustrated in FIG. 2D), wherein two adjacent side surfaces of each of the plurality of active regions (ACT) define an acute angle (see Fig.7 wherein top side surface of active pattern form acute angles with side surfaces), and wherein at least a portion of at least one of the plurality of insulating structures (ST_TR2) is between a corresponding pair of the plurality of active regions (ACT) and between a corresponding pair of the plurality of device isolation layers (ST_TR1) and overlaps the corresponding pair of the plurality of active regions (ACT) in the first horizontal direction (see, for example, Fig.16B).
With respect to claim 2, An discloses, in Figs.1A-18D, the semiconductor device, wherein the plurality of device isolation layers (IL, ST_TR1) and the insulating structures (ST_TR2) extend into a substrate (100), and wherein lower surfaces of the insulating structure (ST_TR2) are at a lower level than lower surfaces of the plurality of device isolation layers (IL, ST_TR1) (see Fig.16B).
With respect to claim 3, An discloses, in Figs.1A-18D, the semiconductor device, wherein the plurality of active regions (ACT) include first side surfaces and second side surfaces spaced apart from each other in the first horizontal direction, and wherein the first side surfaces and the second side surfaces are inwardly curved surfaces (see Figs.5, 11 Par.[0047]-[0048] wherein ACT inward curve are shown).
With respect to claim 4, An discloses, in Figs.1A-18D, the semiconductor device, wherein, in a plan view, the plurality of insulating structures (IL, ST_TR1) have a circular shape (see Fig.15, Par.[0071]-[0072]).
With respect to claim 5, An discloses, in Figs.1A-18D, the semiconductor device, wherein a portion of at least one of the plurality of insulating structures (ST_TR2) overlaps one or more of the plurality of device isolation layers (IL, ST_TR1) in the first horizontal direction (see Figs.15, 16A-16C).
With respect to claim 6, An discloses, in Figs.1A-18D, the semiconductor device, wherein maximum horizontal width of the plurality of insulating structure are greater than horizontal widths of the plurality of active regions in the second horizontal direction (see Fig.15).
With respect to claim 7, An discloses, in Figs.1A-18D, the semiconductor device, wherein the plurality of insulating structures (ST_TR2) are configured as a single layer (see Figs.15, 16A-16C).
With respect to claim 8, An discloses, in Figs.1A-18D, the semiconductor device, wherein the first horizontal direction is a major axis-direction of the plurality of active regions (ACT), and wherein the second horizontal direction is a minor axis-direction of the plurality of active regions (see Figs.15, 16A-16C).
With respect to claim 9, An discloses, in Figs.1A-18D, the semiconductor device, wherein the plurality of device isolation layers include a plurality of first device isolation layers and a plurality of second device isolation layers alternating in the second horizontal direction (see Figs.15, 16A-16C).
With respect to claim 15, An discloses, in Figs.1A-18D, the semiconductor device, wherein a lower surface of the gate structure includes a first portion in contact with the plurality of device isolation layers and a second portion having a width greater than a width of the first portion and in contact with corresponding ones of the plurality of insulating structures, and wherein the second portion is at a higher level than the first portion (see Figs.15, 16A-16C).
With respect to claim 20, An discloses, in Figs.1A-18D, a semiconductor device, comprising: a first active region (ACT) and a second active region (ACT) extending in a first horizontal direction and spaced apart from each other in the first horizontal direction; a first device isolation layer (IL, ST_TR1) and a second device isolation layer (IL, ST_TR1) spaced apart from each other in a second horizontal direction intersecting the first horizontal direction, the first device isolation layer (IL, ST_TR1) and the second device isolation layer (IL, ST_TR1) extending in the first horizontal direction, the first active region (ACT) and the second active region (ACT) interposed between the first device isolation layer (IL, ST_TR1) and the second device isolation layer (IL, ST_TR1); an insulating structure (ST_TR2) between the first active region and the second active region and in contact with the first active region and the second active region; a gate structure (GE) extending in a third horizontal direction between the first horizontal direction and the second horizontal direction and intersecting the first active region; and a bitline structure (BL) intersecting the first active region and extending in a fourth horizontal direction orthogonal to the third horizontal direction, wherein a side surface (ACT_3) of the first active region in contact with the insulating structure is a curved surface recessed toward a central portion of the first active region, and wherein at least a portion of the insulating structure is between the first active region and the second active region and between the first device isolation layer and the second device isolation layer, and overlaps the first active region in the first horizontal direction (see Par.[0023]-[0024] wherein the device isolation layer ST may fill the first and second trenches TR1 and TR2 between the active patterns ACT; see Par.[0028]-[0029] wherein gate electrodes GE may be provided to run (i.e., extend) across the active patterns ACT and the device isolation layer ST; the gate electrodes GE may be provided in corresponding third trenches TR3, as illustrated in FIG. 2D; see Fig.7 wherein top side surface of active pattern form acute angles with side surfaces; see Figs.5, 11 Par.[0047]-[0048] wherein ACT inward curve are shown).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US 2011/0223731 A1 hereinafter referred to as “Chung”) in view of Choi.
With respect to claim 1, Chung discloses, in Figs.1-42B, a semiconductor device, comprising: a plurality of device isolation layers (620) extending in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a plurality of active regions (610, 615) between the plurality of device isolation layers (620) and spaced apart from each other in the first horizontal direction; and a gate structure (665, 680) extending in a third horizontal direction between the first horizontal direction and the second horizontal direction and intersecting the plurality of active regions (see Par.[0110]-[0111] wherein the active layer 610 and the device isolation layer 620 may dry-etched without an etch selectivity to be recessed; according to the recession of the active layer 610 and the device isolation layer 620, a buried bitline pattern 644 may be formed to provide a region where the vertical channels 615 are arranged in a zigzag pattern); a plurality of insulating structures (650, 638) between the plurality of active regions (610, 615) (see Par.[0110] wherein a gate dielectric layer 650 may be formed to surround the vertical channels 615; see Par.[0112] wherein a wordline plug-in 680 may be formed by deposition and recession of a gap-fill insulating layer 638, and deposition and etch-back of a conductive material to connect the gate electrodes 665), and wherein at least a portion of at least one of the plurality of insulating structures (650, 638) is between a corresponding pair of the plurality of active regions (610, 615) and between a corresponding pair of the plurality of device isolation layers (620) and overlaps the corresponding pair of the plurality of active regions (610, 615) in the first horizontal direction (see Figs.39A-39B). However, Chung does not explicitly disclose wherein two adjacent side surfaces of each of the plurality of active regions define an acute angle.
Choi discloses, in Figs.1-24, a semiconductor device, comprising: a plurality of device isolation layers (63) extending in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a plurality of active regions (45) between the plurality of device isolation layers (63) and spaced apart from each other in the first horizontal direction; a plurality of insulating structures (65) between the plurality of active regions (45); and a gate structure (67) extending in a third horizontal direction between the first horizontal direction and the second horizontal direction and intersecting the plurality of active regions (45) (see Par.[0041] wherein referring to FIGS. 1 and 2, a plurality of parallel-trenches 41 and intersect-trenches 49 by which a plurality of active regions 45 are confined may be formed in the semiconductor substrate 21; a device isolation layer 63 filling the parallel-trenches 41 and the intersect-trenches 49 may be formed; a plurality of word lines 67 intersecting the active regions 45 and the device isolation layer 63 may be formed; a gate dielectric layer 65 may be formed between the word lines 67 and the active regions 45), wherein two adjacent side surfaces (S1-S2 and S3-S4) of each of the plurality of active regions (45) define an acute angle (see Par.[0046]-[0049] wherein as illustrated in FIG. 3, the first acute angle .theta.1 may be interpreted as a crossing angle between the second side surface S2 and the bit line 75, and the second acute angle .theta.2 may be interpreted as a crossing angle between the second side surface S2 and the third side surface S3; the first end 45E1 may protrude away from the bit line 75; the second end 45E2 may protrude away from the bit line 75; each of the first end 45E1 and the second end 45E2 may be connected corresponding one of the buried contact plugs (reference number 83 of FIG. 1)), and wherein at least a portion of at least one of the plurality of insulating structures (65) is between a corresponding pair of the plurality of active regions (45) and between a corresponding pair of the plurality of device isolation layers (63) and overlaps the corresponding pair of the plurality of active regions (45) in the first horizontal direction (see Figs.1-2, for insulating 65 between and overlapping active regions 45).
Chung and Choi are analogous art because they are all directed to a semiconductor memory device, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Chung to include Choi because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the pattern of active regions in Chung by including active regions side surfaces forming an angle as taught by Choi in order to utilize the advantages offered by the active regions pattern with acute angle in semiconductor memory such as: improved electrical performance, enhance device reliability, and optimize manufacturing process.
With respect to claim 4, Chung discloses, in Figs.1-42B, the semiconductor device, wherein, in a plan view, the plurality of insulating structures (650, 638) have a circular shape (see Figs.39A-39B).
With respect to claim 5, Chung discloses, in Figs.1-42B, the semiconductor device, wherein a portion of at least one of the plurality of insulating structures (650, 638) overlaps one or more of the plurality of device isolation layers (620) in the first horizontal direction (see Figs.39A-39B).
With respect to claim 6, Chung discloses, in Figs.1-42B, the semiconductor device, wherein maximum horizontal width of the plurality of insulating structure are greater than horizontal widths of the plurality of active regions in the second horizontal direction (see Figs.39A-39B).
With respect to claim 8, Chung discloses, in Figs.1-42B, the semiconductor device, wherein the first horizontal direction is a major axis-direction of the plurality of active regions, and wherein the second horizontal direction is a minor axis-direction of the plurality of active regions (see Figs.39A-39B).
With respect to claim 9, Chung discloses, in Figs.1-42B, the semiconductor device, wherein the plurality of device isolation layers include a plurality of first device isolation layers and a plurality of second device isolation layers alternating in the second horizontal direction (see Figs.39A-39B).
With respect to claim 10, Chung discloses, in Figs.1-42B, the semiconductor device, wherein ends of the plurality of first device isolation layers taken in the first horizontal direction are in a zigzag pattern with ends of the plurality of second device isolation layers taken in the first horizontal direction (see Par.[0110]-[0111] wherein the active layer 610 and the device isolation layer 620 may dry-etched without an etch selectivity to be recessed; according to the recession of the active layer 610 and the device isolation layer 620, a buried bitline pattern 644 may be formed to provide a region where the vertical channels 615 are arranged in a zigzag pattern).
With respect to claim 11, Chung discloses, in Figs.1-42B, the semiconductor device, wherein a maximum width of each of the plurality of insulating structures in the second horizontal direction is proportional to a distance between two adjacent device isolation layers among the plurality of device isolation layers in the second horizontal direction.
Even though Chung does not explicitly disclose a range a maximum width of each of the plurality of insulating structures in the second horizontal direction is equal to a distance between two adjacent device isolation layers among the plurality of device isolation layers in the second horizontal direction, the said range is predictable by simple engineering optimization motivated by a design choice, such as overall electrical conductivity of the device. In cases like the present, where patentability is said to be based upon particular chosen dimensions or upon another variable recited within the claims, applicant must show that the chosen dimensions are critical. As such, the claimed dimensions appear to be an obvious matter of engineering design choice and thus, while being a difference, does not serve in any way to patentably distinguish the claimed invention from the applied prior art. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Kuhle, 526 F2d. 553,555,188 USPQ 7, 9 (CCPA 1975).
With respect to claim 12, Chung discloses, in Figs.1-42B, the semiconductor device, wherein, in a plan view, the plurality of active regions have a rhombic shape (see Figs.39A-39B).
With respect to claim 13, Chung discloses, in Figs.1-42B, the semiconductor device, wherein the plurality of insulating structures (650, 638) intersect the plurality of active regions (610, 615) and the plurality of device isolation layers (620) and extends in a horizontal direction (see Figs.39A-39B).
With respect to claim 14, Chung discloses, in Figs.1-42B, the semiconductor device, wherein, in a plan view, the plurality of insulating structures have a rhombic shape (see Figs.39A-39B).
With respect to claim 15, Chung discloses, in Figs.1-42B, the semiconductor device, wherein a lower surface of the gate structure (690) includes a first portion (680) in contact with the plurality of device isolation layers (620) and a second portion (665) having a width greater than a width of the first portion and in contact with corresponding ones of the plurality of insulating structures (650, 638), and wherein the second portion is at a higher level than the first portion (see Figs.39A-39B).
With respect to claim 16, Chung discloses, in Figs.1-42B, a semiconductor device, comprising: a plurality of device isolation layers (620) extending in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a plurality of active regions (610, 615) between the plurality of device isolation layers and spaced apart from each other in the first horizontal direction (see Par.[0110]-[0111] wherein the active layer 610 and the device isolation layer 620 may dry-etched without an etch selectivity to be recessed; according to the recession of the active layer 610 and the device isolation layer 620, a buried bitline pattern 644 may be formed to provide a region where the vertical channels 615 are arranged in a zigzag pattern); a plurality of insulating structures (650, 638) between the plurality of active regions (610, 615) (see Par.[0110] wherein a gate dielectric layer 650 may be formed to surround the vertical channels 615; see Par.[0112] wherein a wordline plug-in 680 may be formed by deposition and recession of a gap-fill insulating layer 638, and deposition and etch-back of a conductive material to connect the gate electrodes 665); and a gate structure (690) extending in a third horizontal direction between the first horizontal direction and the second horizontal direction and intersecting the plurality of active regions (610, 615) (see Par.[0112]-[0113] wherein a wordline 690 may be implemented), wherein at least a portion of at least one of the plurality of insulating structures (650, 638) is between a corresponding pair of the plurality of active regions and between a corresponding pair of the plurality of device isolation layers and overlaps the corresponding pair of the plurality of active regions in the first horizontal direction, wherein the plurality of insulating structures each include an external insulating layer (636) and an internal insulating layer (650) in the external insulating layer, and wherein the external insulating layer is in contact with a corresponding pair of the plurality of active regions (615) and a corresponding pair of the plurality of device isolation layers (620) (see Par.[0110] wherein a passivation layer 636 is disclosed; see Par.[0081] wherein the passivation layer may be formed in the form of liner by, for example, conformally depositing silicon oxide or silicon nitride; a gate dielectric layer 650 may be formed to surround the vertical channels 615). However, Chung does not explicitly disclose wherein two adjacent side surfaces of each of the plurality of active regions define an acute angle.
Choi discloses, in Figs.1-24, a semiconductor device, comprising: a plurality of device isolation layers (63) extending in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a plurality of active regions (45) between the plurality of device isolation layers (63) and spaced apart from each other in the first horizontal direction; a plurality of insulating structures (65) between the plurality of active regions (45); and a gate structure (67) extending in a third horizontal direction between the first horizontal direction and the second horizontal direction and intersecting the plurality of active regions (45) (see Par.[0041] wherein referring to FIGS. 1 and 2, a plurality of parallel-trenches 41 and intersect-trenches 49 by which a plurality of active regions 45 are confined may be formed in the semiconductor substrate 21; a device isolation layer 63 filling the parallel-trenches 41 and the intersect-trenches 49 may be formed; a plurality of word lines 67 intersecting the active regions 45 and the device isolation layer 63 may be formed; a gate dielectric layer 65 may be formed between the word lines 67 and the active regions 45), wherein two adjacent side surfaces (S1-S2 and S3-S4) of each of the plurality of active regions (45) define an acute angle (see Par.[0046]-[0049] wherein as illustrated in FIG. 3, the first acute angle .theta.1 may be interpreted as a crossing angle between the second side surface S2 and the bit line 75, and the second acute angle .theta.2 may be interpreted as a crossing angle between the second side surface S2 and the third side surface S3; the first end 45E1 may protrude away from the bit line 75; the second end 45E2 may protrude away from the bit line 75; each of the first end 45E1 and the second end 45E2 may be connected corresponding one of the buried contact plugs (reference number 83 of FIG. 1)), and wherein at least a portion of at least one of the plurality of insulating structures (65) is between a corresponding pair of the plurality of active regions (45) and between a corresponding pair of the plurality of device isolation layers (63) and overlaps the corresponding pair of the plurality of active regions (45) in the first horizontal direction (see Figs.1-2, for insulating 65 between and overlapping active regions 45).
Chung and Choi are analogous art because they are all directed to a semiconductor memory device, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Chung to include Choi because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the pattern of active regions in Chung by including active regions side surfaces forming an angle as taught by Choi in order to utilize the advantages offered by the active regions pattern with acute angle in semiconductor memory such as: improved electrical performance, enhance device reliability, and optimize manufacturing process.
With respect to claim 17, Chung discloses, in Figs.1-42B, the semiconductor device, wherein a horizontal width of the external insulating layer (636) is less than half of a horizontal width of a corresponding one of the device isolation layers (620) in the second horizontal direction (see Figs.39A-39B).
With respect to claim 18, Chung discloses, in Figs.1-42B, the semiconductor device, wherein a lower end of the internal insulating layer is on a lower level than a lower end of the external insulating layer (see Figs.39A-39B).
With respect to claim 19, Chung discloses, in Figs.1-42B, the semiconductor device, wherein the external insulating layer and the internal insulating layer extend in a horizontal direction parallel to each other between a corresponding pair of the plurality of active regions (see Figs.39A-39B).
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
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