DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election without traverse of Species A of Invention I directed to Figs. 1A-1B (Claims 1-14) in the reply filed on June 16th, 2026 is acknowledged.
Claims 15-33 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kwon et al. (Pub. No.: US 2023/0048180 A1), hereinafter as Kwon.
Regarding claim 1, Kwon discloses a semiconductor device Figs. 2, 8-9 comprising: a first conductive line (a conductive line 120) (see Fig. 9 and [0028], [0088]); a second conductive line (a conductive line 260) located over the first conductive line (see Fig. 9 and [0090]), wherein the first conductive line (conductive line 120 extends in X direction) and the second conductive line (conductive line 260 extends in Y direction) extend in different directions, intersecting each other (see Figs. 2, 9 and [0090]); a variable resistance pattern (variable resistance layer 144 in MC1) located between the first conductive line and the second conductive line (see Figs. 8-9 and [0034], [0081], [0088]); a first electrode pattern (layer 142 in MC1) located between the first conductive line and the variable resistance pattern (see Figs. 8-9 and [0034], [0051]); a first resistivity barrier pattern (bottom electrode BE1 includes WSiN) located between the first conductive line and the first electrode pattern (see Figs. 8-9 and [0034-0035]); and a first diffusion barrier pattern (combination of middle electrode ME1 and switching element 130) located between the first resistivity barrier pattern and the first electrode pattern (see Figs. 8-9 and [0034-0037]).
Regarding claim 2, Kwon discloses the semiconductor device of claim 1, wherein the first diffusion barrier pattern includes tungsten nitride (WN) or titanium nitride (TiN) (combination of ME1/130 includes Middle electrode ME1 having WN or TiN) (see Fig. 8 and [0035]).
Regarding claim 3, Kwon discloses the semiconductor device of claim 1, wherein the first resistivity barrier pattern includes WSiN (bottom electrode BE1 includes WSiN) (see Fig. 8 and [0035]).
Regarding claim 4, Kwon discloses the semiconductor device of claim 2, wherein the first diffusion barrier pattern prevents an element (W or Si or N from WSiN of BE1) included in the first resistivity barrier pattern from being diffused into the variable resistance pattern (ME1/130 having WN or TiN block elements of BE1 diffusing into variable resistance layer 144) (see Fig. 8 and [0035]).
Regarding claim 5, Kwon discloses the semiconductor device of claim 4, wherein the element includes tungsten, silicon, or both (W or Si or N from WSiN of BE1) (see Fig. 8 and [0035]).
Regarding claim 6, Kwon discloses the semiconductor device of claim 1, wherein a resistivity of the first diffusion barrier pattern is lower than a resistivity of the first resistivity barrier pattern (resistivity of WN of ME1 is lower than resistivity of WSiN of BE1) (see Fig. 8 and [0035]).
Regarding claim 7, Kwon discloses the first resistivity barrier pattern has a first thickness (thickness of BE1), and the first diffusion barrier pattern has a second thickness (thickness of ME1 and layer 130) that is greater than the first thickness (because ME1 and BE1 have similar thicknesses) (see Fig. 8 and [0035]).
Regarding claim 8, Kwon discloses the semiconductor device of claim 1, further comprising: a second electrode pattern (layer 146 in MC1) located between the variable resistance pattern and the second conductive line (see Figs. 8-9 and [0034], [0051]); a second resistivity barrier pattern (bottom electrode BE2 being same as BE1 includes WSiN) located between the second electrode pattern and the second conductive line (see Figs. 8-9 and [0034-0035], [0088]); and a second diffusion barrier pattern (combination of electrode TE1 and conductive line 160 includes WN/TiN) located between the second electrode pattern and the second resistivity barrier pattern (see Figs. 8-9 and [0032], [0035], [0088]).
Regarding claim 9, Kwon discloses the semiconductor device of claim 8, wherein the second diffusion barrier pattern includes tungsten nitride (WN) or titanium nitride (TiN) (combination of electrode TE1 and conductive line 160 includes WN or TiN) (see Figs. 8-9 and [0032], [0035], [0088]).
Regarding claim 10, Kwon discloses the semiconductor device of claim 8, wherein the second resistivity barrier pattern includes WSiN (bottom electrode BE2 being same as BE1 includes WSiN) (see Figs. 8-9 and [0034-0035], [0088]).
Regarding claim 11, Kwon discloses the semiconductor device of claim 8, wherein the second diffusion barrier pattern prevents an element (W or Si or N from WSiN of BE2 as same as BE1) included in the second resistivity barrier pattern from being diffused into the variable resistance pattern (TE1/160 block elements of BE2 diffusing into variable resistance layer 144) (see Fig. 8 and [0032], [0035], [0088]).
Regarding claim 12, Kwon discloses the semiconductor device of claim 8, wherein a resistivity of the second diffusion barrier pattern is lower than a resistivity of the second resistivity barrier pattern (resistivity of WN of TE1/160 is lower than resistivity of WSiN of BE2) (see Fig. 8 and [0032], [0035], [0088]).
Regarding claim 13, Kwon discloses the semiconductor device of claim 8, wherein the second resistivity barrier pattern has a third thickness (thickness of BE2), and the second diffusion barrier pattern has a fourth thickness (thickness of TE1 and conductive line 160) that is greater than the third thickness (see Fig. 8 and [0032], [0035], [0088]).
Regarding claim 14, Kwon discloses a manufacturing method of a semiconductor device in Figs. 8-14, the manufacturing method comprising: forming a first resistivity barrier layer (layer BEL to form BE1) over a first conductive layer (conductive line 120) (see Fig. 9, 11 and [0028], [0088], [0097-0100]); forming a first diffusion barrier layer (combination of layer 130L and layer MEL to form electrode layer 130 and electrode ME1) over the first resistivity barrier layer (see Figs. 8-9, 11-12 and [0034-0037], [0088], [0097-0100]); forming a first electrode layer (layer 142L to form layer 142) over the first diffusion barrier layer (see Figs. 8-9, and [0034], [0051], [0097]); forming a variable resistance layer (variable resistance layer 144L to form layer 144) over the first electrode layer (see Figs. 8-9, 11-12 and [0034], [0081], [0088], [0097]); forming a second electrode layer (layer 146L to form layer 146) over the variable resistance layer (see Figs. 8-9, 11-12 and [0034], [0051], [0097]); and forming a second conductive layer (forming a conductive line 260) over the second electrode layer (see Figs. 8-9, 14 and [0090]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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