DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim(s) 8-20 have been cancelled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 21-26 and 28-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 20060120175 to Chou et al. (“Chou”) in view of U.S. Patent/Publication No. 20200388333 to Lin et al. (“Lin”).
As to claim 1, Chou teaches substantially the claimed invention, including, but not limited to: An apparatus (As found in at least FIG. 6)comprising: a first transistor coupling a supply voltage to a bitline (As found in at least FIGS. 1-3: 55 couples VDD to bitline BL#), wherein the first transistor is configured to precharge the bitline (As found in at least FIG. 3 and [0009], precharge current is provided to BL# by 55); a detector having an input coupled to the bitline (As found in at least FIG. 3: detector 52, an input of which is coupled to bitline BL#), wherein the detector is configured to detect whether a first memory cell has reached a threshold (As found in at least FIGS. 2-3 and at least [0008]: At this point, the precharge step is completed, and the bit line is ready for sensing. Upon accessing a memory cell, the cell data influences the voltage at the node V.sub.CELL, causing it to move quickly toward a high cell threshold value V.sub.CELL.sub.--.sub.HVT or toward a low cell threshold value V.sub.CELL.sub.--.sub.LVT; wherein, as found in [0008], detector 52 detects whether cell data has reached a threshold, as given by at least Vref).
While the teachings of Lin, relevantly and complementarily, further teach well-know and well-understood design considerations in the relevant art. For example, at least FIG. 5 teaches precharging bit lines BL# to a voltage potential using a transistor in 310; while also teaching that associated source lines receive similar precharging voltages using a transistor, also in 310; that is, commonly, both bit lines and source lines associated with a memory cell 12, receive precharging voltages from a voltage source using transistors; also, and similarly, sensing lines directly associated and coupled to memory cells are also precharged in advance of sensing, detecting memory cell data state: this precharging is also achieved by means of a transistor 120 and t-gate coupled thereto both coupled to a voltage source VDD; the teachings of Lin also consider the use of a detector 200 to detect the state (current level) of a memory cell 12 by sensing the current cell through a second transistor 212 that establishes a voltage sensing level at an input of the detector 200.
Chou and Lin are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory having cell data state detectors detecting current of cells on bit lines coupled to said detector.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Chou as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Lin also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: memory having cell data state detectors detecting current of cells on bit lines coupled to said detector.
Therefore, it would have been obvious to combine Chou with Lin to make the above modification.
As to claim 2, Lin teaches a second transistor coupling the input of the detector to the bitline, wherein the second transistor is configured to change a voltage of the detector input when the first memory cell reaches the threshold (As found in at least FIG. 3: 51; and [0009]: Transistor 54 is a transistor having a higher threshold voltage than the clamp transistor 51. The higher threshold is achieved for example by making transistor 54 with a narrower and longer channel region. Therefore, during a precharge interval precharge paths are provided both through the load 50 and the transistor 55. Both transistors 54 and 51 will be on while the voltage on the bit line V.sub.BL is low. As the voltage on the bit line V.sub.BL approaches V.sub.BIAS (less the threshold of transistor 54, including body effects), transistor 54 will turn off first because of its higher threshold voltage, and disable the precharge path through transistor 55. Dynamic balance will be achieved between the load 50 and the clamp transistor 51 as described above, settling the sensing node at the target level; moreover, as found in at least [0008]: Upon accessing a memory cell (53), the cell data influences the voltage at the node V.sub.CELL: that is 51 is “configured” to change a voltage input, Vcell, of the detector; the memory cell 51 is either in a “low” state or “high” state: thus reaching a threshold to be detected); wherein the second transistor is in an off state at an end of the first transistor precharging the bitline (As found in at least FIGS. 4A-4B, 5: second transistor, coupled to signal P1, is off at end of first transistor, coupled to signal P2, precharging the bitline).
As to claim 3, Chou teaches wherein the first transistor is in an on state when precharging the bitline, and is in an off state when the detector is detecting whether the first memory cell has reached the threshold (As found in at least FIG. 3 and at least [0009]).
As to claim 4, Chou teaches wherein the first transistor is a p-channel device, and the second transistor is an n-channel device (As found in at least FIG. 3: 55 is a p-channel and 51 is an n-channel; moreover, whether a transistor is p-channel or n-channel is not an inventive configuration; a p-channel is complementary to an n-channel, and one can be replaced by the other by merely reversing biasing polarities, well-know, well-understood basic, and fundamental functionality).
As to claim 5, Chou teaches wherein a first current terminal of the first transistor is coupled to a gate of the second transistor, and a second current terminal of the first transistor is coupled to the bitline (As found in at least FIG. 3 and at least [0030]).
As to claim 6, Chou teaches current source is-configured to drive the input of the detector to the supply voltage (As found in at least FIG. 3: current source 50 drives input of 52 to supply voltage VDD).
As to claim 7, Chou teaches wherein the first transistor is configured to precharge the bitline to the supply voltage (As found in at least FIG. 3: 55 is configured to precharge bit line BL# to supply voltage VDD).
As to claim(s) 21-22, see rejection to at least claim(s) 1-2; moreover, the method is inherently taught by the apparatus. While at least Chou teaches providing a reference current to set a voltage of the input of the detector (As found in at least FIG. 3: current source rom 50 at input to detector 52).
As to claim 23, Chou teaches coupling, by a first transistor, a supply voltage to the bitline, and coupling, by a second transistor, the input of the detector to the bitline (As found in at least FIG. 3: first transistor: one of at least 55 and 54, coupling VDD to bitline BL#; second transistor 51 coupling input to 52 to bitline BL#).
As to claim 24, Chou teaches wherein the first transistor is in parallel with the second transistor (As found in at least FIG. 3: one of at least 55 and 54 is in parallel with 51).
As to claim 25, Chou teaches wherein the second transistor is a cascode transistor (As found in at least FIG. 3: 51 is a cascode transistor: on top of another transistor).
As to claim 26, Chou teaches a voltage regulator, wherein the supply voltage is provided by the voltage regulator (As found in at least FIG. 6 and at least [0041]: voltage regulator 608).
As to claim 28, Chou teaches comparing a cell current of the memory cell with a reference current (As found in at least FIG. 3: cell 53 data is compared against reference Vref).
As to claim 29, Chou teaches a current source coupled to provide a reference current to set a voltage of the input of the detector (As found in at least FIG. 3: source 50 provides a reference to set a voltage at input of 52).
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 20060120175 to Chou et al. (“Chou”) in view of U.S. Patent/Publication No. 20200388333 to Lin et al. (“Lin”), and further in view of TW 202030731 A to Arsovski et al. (“Arsovski”).
As to claim 27, while at least Lin teaches process reset for a next cycle operation. Additionally, relevantly and complementarily, Arsovski teaches resetting the detector in preparation for a sensing operation to sense the memory cell (“For example, when reading rows 0, 1, and 2, the sense amplifier can perform a reset operation to clear the previous read operation and make the sense amplifier in a known state suitable for sensing”).
Chou as modified and Arsovski are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory having cell data state detectors detecting current of cells on bit lines coupled to said detector.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Chou as modified as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Arsovski also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: as provided by the teachings of Arsovski: the sense amplifier can perform a reset operation to clear the previous read operation and make the sense amplifier in a known state suitable for sensing.
Therefore, it would have been obvious to combine Chou as modified with Arsovski to make the above modification.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827
Prosecution Insights