DETAILED ACTION
This Office Action is responsive to the Applicant’s communication filed 13 December 2023. In view of this communication, claims 1-20 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-6, 7-10, 12-14, 16, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shimizu et al. (US 20180166372 A1), hereinafter referred to as Shimizu et al., in view of Hwang et al., hereinafter referred to as Hwang et al. (US 20220071016 A1).
Regarding claim 1, Shimizu et al. teaches a printed wiring board, comprising:
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a laminate (12) comprising a plurality of resin insulating layers (61, 63, 65) (paragraphs 27 and 44: wiring structure 12 comprising insulating layers 61, 63, and 65; paragraph 109: resin films 61, 63, and 65 are laminated to the upper surface of insulating layer 31) and a plurality of conductor layers (50, 70, 80, 90) (paragraph 47: wiring layers 50, 70, 80, 90); and
a plurality of via conductors (61X, 63X, 65X) formed in via holes of the resin insulating layers (61, 63, 65) (paragraphs 57, 63, and 69-70: through holes 61X, 63X, and 65X to connect the wiring layers 50, 70, 80, and 90) and each comprising a seed layer (paragraphs 49, 59, 65, and 72: each wiring layer 50, 70, 80, and 90 comprises a seed layer 51, 71, 81, and 91 that extends into the vias 61X, 63X, and 65X) and an electrolytic plating layer (54, 74, 84, 94) formed on the seed layer such that the via conductors connect the conductor layers adjacent to each other (paragraphs 101, 111, 113, and 114: seed layers 54, 74, 84, and 94 are formed on seed layers 51, 71, 81, and 91, respectively) and that the via conductors (61X, 63X, 65X) include a first via conductor (61X) and a second via conductor (63X) formed on the first via conductor (61X) in a lamination direction of the laminate (12) (see Fig. 1),
wherein the resin insulating layers (61, 63, 65) include resin and inorganic particles (paragraph 45: insulating layers 61, 63, 65 comprise a filler such as silica or alumina).
Shimizu et al. does not teach that the inorganic particles include first inorganic particles having smooth surfaces and second inorganic particles embedded in the resin insulating layers and that an inner wall surface of each of the via holes in the resin insulating layers includes the resin and the smooth surfaces of the first inorganic particles.
Hwang et al. does teach that the inorganic particles include first inorganic particles having smooth surfaces and second inorganic particles embedded in the resin insulating layers and that an inner wall surface of each of the via holes (VH) in the resin insulating layers (311) includes the resin (311) and the smooth surfaces of the first inorganic particles (312) (Hwang et al. Fig. 13 and paragraph 29: the inorganic particles 312 are cut and exposed on the surface of the via VH).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the vias of Shimizu et al. such that an inner wall surface of each of the via holes in the resin insulating layers includes the resin and the smooth surfaces of the first inorganic particles because the resin of Hwang et al. with the exposed inorganic particles improves peel strength between the resin and conductor layers of the via (Hwang paragraph 36).
Regarding claim 2, Shimizu et al. in view of Hwang et al. teaches the printed wiring board according to claim 1, wherein the laminate is formed such that the smooth surfaces of the first inorganic particles are cut surfaces of the inorganic particles (Hwang et al. Fig. 13 and paragraph 29: the inorganic particles 312 are cut and exposed on the surface of the via VH).
Regarding claim 3, Shimizu et al. in view of Hwang et al. teaches the printed wiring board according to claim 1, wherein the laminate is formed such that a surface of the resin and the smooth surfaces on the inner wall surface are flush with each other (Hwang et al. Fig. 13 and paragraph 29: the inorganic particles 312 are cut and exposed on the surface of the via VH, resulting in a surface of the via VH that consists of particle surfaces and resin which are flush).
Regarding claim 4, Shimizu et al. in view of Hwang et al. teaches the printed wiring board according to claim 1, wherein the plurality of via conductors (61X, 63X, 65X) is formed such that the seed layer (52, 72, 82, 92) in each of the via conductors (61X, 63X, 65X) is a sputtering film (Shimizu et al. paragraphs 50, 59, 65, and 72: the seed layer 52 is formed by sputtering and the seed layers 72, 82, and 92 are formed in a similar fashion).
Regarding claim 5, Shimizu et al. in view of Hwang et al. teaches the printed wiring board according to claim 4, wherein the plurality of via conductors (61X, 63X, 65X) is formed such that the sputtering film (51, 71, 81) in each of the via conductors (61X, 63X, 65X) includes a first layer (52, 72, 82, 92) in contact with the inner wall surface of each of the via holes (61X, 63X, 65X) and a second layer (53, 73, 83, 93) formed on the first layer (52, 72, 82, 92) (Shimizu et al. paragraphs 50, 59, 65, and 72: each seed layer 51, 71, 81, 91 comprises a lower layer 52, 72, 82, 92, in contact with the surfaces of the through hole, and an upper layer 53, 73, 83, 93, that covers the upper surface of the respective lower layers 52, 72, 82, 92).
Regarding claim 7, Shimizu et al. in view of Hwang et al. teaches the printed wiring board according to claim 4, wherein the plurality of via conductors (61X, 63X, 65X) is formed such that the sputtering film (51, 71, 81, 91) in each of the via conductors (61X, 63X, 65X) includes a first layer (52, 72, 82, 92) comprising a copper alloy in contact with the inner wall surface of each of the via holes and a second layer (53, 73, 83, 93) comprising copper formed on the first layer (52, 72, 82, 92) (Shimizu et al. paragraphs 50, 59, 65, and 72: each seed layer 51, 71, 81, 91 comprises a lower layer 52, 72, 82, 92, in contact with the surfaces of the through hole, and an upper layer 53, 73, 83, 93, that covers the upper surface of the respective lower layers 52, 72, 82, 92 and each of these layers is formed of copper).
Regarding claim 8, Shimizu et al. in view of Hwang et al. teaches the printed wiring board according to claim 2, wherein the laminate is formed such that a surface of the resin (61, 63, 65) and the smooth surfaces on the inner wall surface are flush with each other (Hwang et al. Fig. 13 and paragraph 29: the inorganic particles 312 are cut and exposed on the surface of the via VH, resulting in a surface of the via VH that consists of particle surfaces and resin which are flush).
Regarding claim 9, Shimizu et al. in view of Hwang et al. teaches the printed wiring board according to claim 2, wherein the plurality of via conductors (61X, 63X, 65X) is formed such that the seed layer (52, 72, 82, 92) in each of the via conductors (61X, 63X, 65X) is a sputtering film (Shimizu et al. paragraphs 50, 59, 65, and 72: the seed layer 52 is formed by sputtering and the seed layers 72, 82, and 92 are formed in a similar fashion).
Regarding claim 10, Shimizu et al. in view of Hwang et al. teaches the printed wiring board according to claim 9, wherein the plurality of via conductors (61X, 63X, 65X) is formed such that the sputtering film (51, 71, 81) in each of the via conductors (61X, 63X, 65X) includes a first layer (52, 72, 82, 92) in contact with the inner wall surface of each of the via holes (61X, 63X, 65X) and a second layer (53, 73, 83, 93) formed on the first layer (52, 72, 82, 92) (Shimizu et al. paragraphs 50, 59, 65, and 72: each seed layer 51, 71, 81, 91 comprises a lower layer 52, 72, 82, 92, in contact with the surfaces of the through hole, and an upper layer 53, 73, 83, 93, that covers the upper surface of the respective lower layers 52, 72, 82, 92).
Regarding claim 12, Shimizu et al. in view of Hwang et al. teaches the printed wiring board according to claim 9, wherein the plurality of via conductors (61X, 63X, 65X) is formed such that the sputtering film (51, 71, 81, 91) in each of the via conductors (61X, 63X, 65X) includes a first layer (52, 72, 82, 92) comprising a copper alloy in contact with the inner wall surface of each of the via holes and a second layer (53, 73, 83, 93) comprising copper formed on the first layer (52, 72, 82, 92) (Shimizu et al. paragraphs 50, 59, 65, and 72: each seed layer 51, 71, 81, 91 comprises a lower layer 52, 72, 82, 92, in contact with the surfaces of the through hole, and an upper layer 53, 73, 83, 93, that covers the upper surface of the respective lower layers 52, 72, 82, 92 and each of these layers is formed of copper).
Regarding claim 13, Shimizu et al. in view of Hwang et al. teaches the printed wiring board according to claim 3, wherein the plurality of via conductors (61X, 63X, 65X) is formed such that the seed layer (52, 72, 82, 92) in each of the via conductors (61X, 63X, 65X) is a sputtering film (Shimizu et al. paragraphs 50, 59, 65, and 72: the seed layer 52 is formed by sputtering and the seed layers 72, 82, and 92 are formed in a similar fashion).
Regarding claim 14, Shimizu et al. in view of Hwang et al. teaches the printed wiring board according to claim 13, wherein the plurality of via conductors (61X, 63X, 65X) is formed such that the sputtering film (51, 71, 81) in each of the via conductors (61X, 63X, 65X) includes a first layer (52, 72, 82, 92) in contact with the inner wall surface of each of the via holes (61X, 63X, 65X) and a second layer (53, 73, 83, 93) formed on the first layer (52, 72, 82, 92) (Shimizu et al. paragraphs 50, 59, 65, and 72: each seed layer 51, 71, 81, 91 comprises a lower layer 52, 72, 82, 92, in contact with the surfaces of the through hole, and an upper layer 53, 73, 83, 93, that covers the upper surface of the respective lower layers 52, 72, 82, 92).
Regarding claim 16, Shimizu et al. in view of Hwang et al. teaches the printed wiring board according to claim 13, wherein the plurality of via conductors (61X, 63X, 65X) is formed such that the sputtering film (51, 71, 81, 91) in each of the via conductors (61X, 63X, 65X) includes a first layer (52, 72, 82, 92) comprising a copper alloy in contact with the inner wall surface of each of the via holes and a second layer (53, 73, 83, 93) comprising copper formed on the first layer (52, 72, 82, 92) (Shimizu et al. paragraphs 50, 59, 65, and 72: each seed layer 51, 71, 81, 91 comprises a lower layer 52, 72, 82, 92, in contact with the surfaces of the through hole, and an upper layer 53, 73, 83, 93, that covers the upper surface of the respective lower layers 52, 72, 82, 92 and each of these layers is formed of copper).
Regarding claim 18, Shimizu et al. in view of Hwang et al. teaches the printed wiring board according to claim 1, wherein the resin insulating layer is formed such that the smooth surfaces of the first inorganic particles have an arithmetic mean roughness Ra of 1.0 µm or less (Shimizu et al. paragraphs 32-33: the filler has a surface roughness of between 0.5 and 1 µm).
Claim(s) 6, 11, 15, 17, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shimizu et al. in view of Hwang et al., in further view of Bahl et al. (US 20180054889 A1), hereinafter referred to as Bahl et al.
Regarding claim 6, Shimizu et al. in view of Hwang et al. teaches the printed wiring board according to claim 1, wherein the laminate is formed such that each of the conductor layers (50, 70, 80, 90) includes a seed layer (51, 71, 81, 91) (paragraphs 49, 59, 65, and 72: each wiring layer 50, 70, 80, and 90 comprises a seed layer 51, 71, 81, and 91) formed on a surface of a respective one of the resin insulating layers (61, 63, 65), and an electrolytic plating layer (54, 74, 84, 94) formed on the seed layer (51, 71, 81, 91) on the surface of the respective one of the resin insulating layers (61, 63, 65) (paragraphs 101, 111, 113, and 114: seed layers 54, 74, 84, and 94 are formed on seed layers 51, 71, 81, and 91, respectively).
Shimizu et al. in view of Hwang et al. does not teach that the surface of the respective one of the resin insulating layers (61, 63, 65) is formed only of the resin. Bahl et al. does teach that the surface (404) of the respective one of the resin insulating layers (402) is formed only of the resin (402) (Bahl et al. Fig. 4 and paragraphs 63-64: particles 414 are distributed between boundaries 408, 25µm away from the surfaces 404 of the resin 402).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the resin insulating layers of Shimizu et al. in view of Hwang et al. such that the surface of the resin insulating layers comprises only resin because exposed particles on the surface of the resin insulating layer could cause unwanted electroplating (Bahl et al. paragraph 64).
Regarding claim 11, Shimizu et al. in view of Hwang et al. teaches the printed wiring board according to claim 2, wherein the laminate is formed such that each of the conductor layers (50, 70, 80, 90) includes a seed layer (51, 71, 81, 91) (paragraphs 49, 59, 65, and 72: each wiring layer 50, 70, 80, and 90 comprises a seed layer 51, 71, 81, and 91) formed on a surface of a respective one of the resin insulating layers (61, 63, 65), and an electrolytic plating layer (54, 74, 84, 94) formed on the seed layer (51, 71, 81, 91) on the surface of the respective one of the resin insulating layers (61, 63, 65) (paragraphs 101, 111, 113, and 114: seed layers 54, 74, 84, and 94 are formed on seed layers 51, 71, 81, and 91, respectively).
Shimizu et al. in view of Hwang et al. does not teach that the surface of the respective one of the resin insulating layers (61, 63, 65) is formed only of the resin. Bahl et al. does teach that the surface (404) of the respective one of the resin insulating layers (402) is formed only of the resin (402) (Bahl et al. Fig. 4 and paragraphs 63-64: particles 414 are distributed between boundaries 408, 25µm away from the surfaces 404 of the resin 402).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the resin insulating layers of Shimizu et al. in view of Hwang et al. such that the surface of the resin insulating layers comprises only resin because exposed particles on the surface of the resin insulating layer could cause unwanted electroplating (Bahl et al. paragraph 64).
Regarding claim 15, Shimizu et al. in view of Hwang et al. teaches the printed wiring board according to claim 3, wherein the laminate is formed such that each of the conductor layers (50, 70, 80, 90) includes a seed layer (51, 71, 81, 91) (paragraphs 49, 59, 65, and 72: each wiring layer 50, 70, 80, and 90 comprises a seed layer 51, 71, 81, and 91) formed on a surface of a respective one of the resin insulating layers (61, 63, 65), and an electrolytic plating layer (54, 74, 84, 94) formed on the seed layer (51, 71, 81, 91) on the surface of the respective one of the resin insulating layers (61, 63, 65) (paragraphs 101, 111, 113, and 114: seed layers 54, 74, 84, and 94 are formed on seed layers 51, 71, 81, and 91, respectively).
Shimizu et al. in view of Hwang et al. does not teach that the surface of the respective one of the resin insulating layers (61, 63, 65) is formed only of the resin. Bahl et al. does teach that the surface (404) of the respective one of the resin insulating layers (402) is formed only of the resin (402) (Bahl et al. Fig. 4 and paragraphs 63-64: particles 414 are distributed between boundaries 408, 25µm away from the surfaces 404 of the resin 402).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the resin insulating layers of Shimizu et al. in view of Hwang et al. such that the surface of the resin insulating layers comprises only resin because exposed particles on the surface of the resin insulating layer could cause unwanted electroplating (Bahl et al. paragraph 64).
Regarding claim 17, Shimizu et al. in view of Hwang et al. teaches the printed wiring board according to claim 4, wherein the laminate is formed such that each of the conductor layers (50, 70, 80, 90) includes a seed layer (51, 71, 81, 91) (paragraphs 49, 59, 65, and 72: each wiring layer 50, 70, 80, and 90 comprises a seed layer 51, 71, 81, and 91) formed on a surface of a respective one of the resin insulating layers (61, 63, 65), and an electrolytic plating layer (54, 74, 84, 94) formed on the seed layer (51, 71, 81, 91) on the surface of the respective one of the resin insulating layers (61, 63, 65) (paragraphs 101, 111, 113, and 114: seed layers 54, 74, 84, and 94 are formed on seed layers 51, 71, 81, and 91, respectively).
Shimizu et al. in view of Hwang et al. does not teach that the surface of the respective one of the resin insulating layers (61, 63, 65) is formed only of the resin. Bahl et al. does teach that the surface (404) of the respective one of the resin insulating layers (402) is formed only of the resin (402) (Bahl et al. Fig. 4 and paragraphs 63-64: particles 414 are distributed between boundaries 408, 25µm away from the surfaces 404 of the resin 402).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the resin insulating layers of Shimizu et al. in view of Hwang et al. such that the surface of the resin insulating layers comprises only resin because exposed particles on the surface of the resin insulating layer could cause unwanted electroplating (Bahl et al. paragraph 64).
Regarding claim 19, Shimizu et al. in view of Hwang et al. teaches the printed wiring board according to claim 1, wherein the laminate is formed such that each of the conductor layers (50, 70, 80, 90) includes a seed layer (51, 71, 81, 91) (paragraphs 49, 59, 65, and 72: each wiring layer 50, 70, 80, and 90 comprises a seed layer 51, 71, 81, and 91) formed on a surface of a respective one of the resin insulating layers (61, 63, 65), and an electrolytic plating layer (54, 74, 84, 94) formed on the seed layer (51, 71, 81, 91) on the surface of the respective one of the resin insulating layers (61, 63, 65) (paragraphs 101, 111, 113, and 114: seed layers 54, 74, 84, and 94 are formed on seed layers 51, 71, 81, and 91, respectively) and that the surface of the respective one of the resin insulating layers has an arithmetic mean roughness Ra in a range of 0.02 µm to 0.06 µm (Shimizu et al. paragraph 110: the roughness of the upper surface of the insulating layers is 10nm or 0.01 µm).
Shimizu et al. in view of Hwang et al. does not teach that the surface of the respective one of the resin insulating layers (61, 63, 65) is formed only of the resin. Bahl et al. does teach that the surface (404) of the respective one of the resin insulating layers (402) is formed only of the resin (402) (Bahl et al. Fig. 4 and paragraphs 63-64: particles 414 are distributed between boundaries 408, 25µm away from the surfaces 404 of the resin 402).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the resin insulating layers of Shimizu et al. in view of Hwang et al. such that the surface of the resin insulating layers comprises only resin because exposed particles on the surface of the resin insulating layer could cause unwanted electroplating (Bahl et al. paragraph 64).
Regarding claim 20, Shimizu et al. in view of Hwang et al. teaches the printed wiring board according to claim 1, wherein the laminate is formed such that the smooth surfaces of the first inorganic particles have an arithmetic mean roughness Ra of 1.0µm or less (Shimizu et al. paragraphs 32-33: the filler has a surface roughness of between 0.5 and 1 µm), that each of the conductor layers (50, 70, 80, 90) includes a seed layer (51, 71, 81, 91) (paragraphs 49, 59, 65, and 72: each wiring layer 50, 70, 80, and 90 comprises a seed layer 51, 71, 81, and 91) formed on a surface of a respective one of the resin insulating layers (61, 63, 65), and an electrolytic plating layer (54, 74, 84, 94) formed on the seed layer (51, 71, 81, 91) on the surface of the respective one of the resin insulating layers (61, 63, 65) (paragraphs 101, 111, 113, and 114: seed layers 54, 74, 84, and 94 are formed on seed layers 51, 71, 81, and 91, respectively) and that the surface of the respective one of the resin insulating has an arithmetic mean roughness Ra in a range of 0.02 µm to 0.06 µm (Shimizu et al. paragraph 110: the roughness of the upper surface of the insulating layers is 10nm or 0.01 µm).
Shimizu et al. in view of Hwang et al. does not teach that the surface of the respective one of the resin insulating layers (61, 63, 65) is formed only of the resin. Bahl et al. does teach that the surface (404) of the respective one of the resin insulating layers (402) is formed only of the resin (402) (Bahl et al. Fig. 4 and paragraphs 63-64: particles 414 are distributed between boundaries 408, 25µm away from the surfaces 404 of the resin 402).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the resin insulating layers of Shimizu et al. in view of Hwang et al. such that the surface of the resin insulating layers comprises only resin because exposed particles on the surface of the resin insulating layer could cause unwanted electroplating (Bahl et al. paragraph 64).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Usui et al. (US 20050263895 A1)
Murai et al. (US 20070082183 A1)
Nakasato et al. (US 20070164349 A1)
Yu (US 20110048783 A1)
Oga et al. (US 20110232953 A1)
Liu (US 8187478 B2)
Harazono et al. (US 20120132462 A1)
Harazono et al. (US 20190132962 A1)
Yukiiri (US 12604395 B2)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John B Freal whose telephone number is (571)272-4056. The examiner can normally be reached Mon-Fri 7:00-3:00.
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/JOHN B FREAL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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