DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The amendment filed on 04/07/2026 has been entered. As of the date of this amendment, the status of the claims is as follows:
Claims 1-20 are pending.
Claim 21 is cancelled.
Claims 1, 8, 10, 11, 13, 17, 19, and 20 have been amended.
An action on the merits for claims 1-20 follows.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
However, should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Specification
Acknowledgement is made of applicant’s replacement of the title of the invention to a new title which is more clearly indicative of the invention to which the claims are directed. The objection to the title is hereby withdrawn.
With respect to the abstract, Examiner maintains the previous objection noted in the NF dated April 7, 2026.
Acknowledgement is made of the amendment to the abstract dated July 7, 2026, which is appreciated. The amendment does result in the abstract having a more narrative format in terms of its sentence structure. It still, however, primarily tracts the structure of the claim, and thus the main focus and nature of the inventive concept and what is new is not readily apparent. Therefore, it may not be clear to a reader whether they need to consult the full patent text for details. Please see MPEP 608.01(b)IIB.
Response to Arguments
Applicant's arguments filed July 7th, 2026 have been fully considered and are persuasive in light of the associated claim amendments. A new rejection has been made to address the newly amended limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-6, 9-13, 15-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US Pub. 2019/0115351 A1), hereinafter Jeon in view of Jeon et al. (US Pub. 2010/0213541 A1), hereinafter Jeon2010 and Thombare et al. (US 20250179635 A1), hereinafter Thombare.
Regarding Claim 1, Jeon teaches a semiconductor memory device (Figs. 1 (plan-view) and 4 (cross-section), Paragraph [0006]), comprising: (Note: Referenced paragraphs may refer to figure 2A when referring to features identical between the embodiments of figures 2A and 4)
a substrate (100) including an element separation film (‘device isolation layer’ (110); Fig. 4, Paragraph [0019]) defining active areas (‘active regions’ (ACT); Paragraph [0019]); and
gate structures (Gate structure components (GL) and (210) are shown to be in the trench ((120); Fig. 4) in trenches (120) on the substrate (100), the gate structures intersecting (‘extend crossing the active regions (ACT); Fig.1, Paragraph [0020]) the active areas (ACT), and each of the gate structures including:
a gate insulating layer (‘gate dielectric layer’ (210); Fig. 4, Paragraph [0027]) extending along sidewalls and a bottom surface of a corresponding one of the trenches (120),
a gate electrode layer (Gate Line (GL) component (230) and (240) together, Paragraph [0021]) on the gate insulating layer (210), the gate electrode layer ((230) and (240) together) including a first metal layer (‘conductive layer’ (230); Paragraph [0021]) and a second metal layer (‘first work function adjusting layer’ (240); Paragraph [0021]) on the first metal layer (230),
a liner film (‘liner layer’ (220); Paragraph [0021]) between the gate insulating layer (210) and the first metal layer (230), the liner film (220) including a same metal material (‘titanium nitride (TiN)’; Paragraph [0022]) as the first metal layer ((230); Paragraph [0023]) and the second metal layer ((240); Paragraph [0024]) and
a capping film (‘first capping layers’ (250); Paragraph [0029]) in contact with the second metal layer (240), and
wherein a lower surface of the second metal layer (240) is in contact with an upper surface of the liner film (220).
Jeon does not explicitly teach wherein each of the first metal layer, the second metal layer, and the liner film includes molybdenum (Mo).
Jeon2010 teaches at least a semiconductor memory device (‘semiconductor device’ (2); Fig. 4, Paragraph [0039]) wherein each of the first metal layer (‘lower buried word line’ (250a); Paragraph [0040]) and the second metal layer (‘upper buried word line,’ (250b); Paragraph [0040]) includes molybdenum (Mo) (“materials for forming the word line 150 illustrated Figs. 2E and 2F may be used to form the lower buried word line 250a and the upper buried word line 250b,” Paragraph [0042]; “the word line 150 may include at least one of […] molybdenum (Mo),” Paragraph [0031]). (Note: Although Paragraph [0040] suggests the two word lines use made of different materials, Paragraph [0031] states that the word line includes at least one material and thus 250a and 250b could both include molybdenum while still using a different material).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Jeon2010 into the device of Jeon such that the semiconductor memory device has a first metal layer and second metal layer comprising molybdenum. This is because the resulting device would have improved efficiency and electrical properties from using a lower resistance material (Paragraph [0031]).
Jeon as modified by Jeon2010 does not explicitly teach wherein the liner film includes molybdenum (Mo).
Thombare teaches at least a semiconductor memory device (“DRAM architecture;” Figs. 2 (trench of DRAM structure), 1A (metallization stacks used in Fig. 2), Paragraphs [0022, 0023]) wherein the liner film (“conformal barrier layer,” (206); Fig. 2A, Paragraph [0028]) includes molybdenum (Mo) (“barrier layers including […] molybdenum carbon nitride;” Paragraph [0024]; Note: both 206 in Fig. 2 and 106 in Fig. 1A are barrier layers and are located at the same spot in the material stacks so are referring to the same material. Fig. 5 (a related method) also shows this).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Thombare into the device of Jeon as modified by Jeon2010 such that the liner film comprises molybdenum. This is because the structure of a molybdenum gate electrode and molybdenum liner film is a metallization stack with low resistance characteristics that can improve efficiency by being applied to a semiconductor device (Paragraph [0023, 0028]).
Regarding Claim 2, Jeon as modified by Jeon2010 and Thombare teaches the semiconductor memory device (Jeon, Fig. 4) as claimed in claim 1, wherein the first metal layer (230) is in contact with an inner side surface of the liner film (220), and the second metal layer (240) is in contact with an upper surface of the liner film (220).
Regarding Claim 3, Jeon as modified by Jeon2010 and Thombare teaches the semiconductor memory device (Jeon, Fig. 4, Paragraph [0018]) as claimed in claim 1, wherein a height of an upper surface of the second metal layer (240) is higher than a height of an upper surface of the liner film (220).
Regarding Claim 5, Jeon as modified by Jeon2010 and Thombare teaches the semiconductor memory device (Jeon, Fig. 4, Paragraph [0018]) as claimed in claim 1, wherein a height of an upper surface of the liner film (220) is lower than a height of an upper surface of the first metal layer (230).
Regarding Claim 6, Jeon as modified by Jeon2010 and Thombare teaches the semiconductor memory device (Jeon, Fig. 4, Paragraph [0018]) as claimed in claim 1, wherein a sum of thicknesses of the first metal layer (230) and the liner film (220) is equal to a thickness of the second metal layer (240) (Paragraphs [0023] and [0024]). (Note: Thickness is here interpreted to be measured from the left trench wall to the right trench wall on a horizontal plane at the given layers widest points given that the trench walls are parallel.)
Regarding Claim 9, Jeon as modified by Jeon2010 and Thombare teaches the semiconductor memory device (Jeon, Fig. 4, Paragraph [0018]) as claimed in claim 1, wherein the first metal layer (230) includes a first metal material (‘titanium (TiN)’; Paragraph [0023]), and the second metal layer (240) includes a second metal material (‘tantalum (Ta)’; Paragraph [0024]).
Regarding Claim 10, Jeon as modified by Jeon2010 and Thombare further teaches the semiconductor memory device (Thombare, Figs. 2, 1, Paragraph [0023]) as claimed in claim 1, wherein the liner film (Thombare, 206) includes a molybdenum compound (“barrier layers including […] molybdenum carbon nitride;” Paragraph [0024]).
Regarding Claim 11, Jeon as modified by Jeon2010 and Thombare further teaches the semiconductor memory device (Jeon2010, ‘semiconductor device’ (2); Fig. 4; Paragraph [0075]) as claimed in claim 9 wherein the liner film (Jeon2010, ‘gate electrode layer’ (140); Figs. 2, 4, Paragraph [0040]) includes a compound (Jeon2010, ‘(Ti/TiN) layer’; Paragraph [0005]) of the first metal material (Jeon2010, ‘(Ti)’; Paragraph [0005]), and a compound (Jeon2010, ‘(Ta/TaN) layer’; Paragraph [0005]) of the second metal material (Jeon2010, ‘(Ta)’; Paragraph [0005]). (Note: the referenced gate electrode layer (140) may include multiple layers including multiple metals and/or metal oxides and all provide materials within a desired resistivity)
Regarding Claim 12, Jeon as modified by Jeon2010 and Thombare teaches the semiconductor memory device (Jeon, Fig. 4, Paragraph [0018]) as claimed in claim 1, further comprising: first source/drain regions (SD1) and second source/drain regions (SD2) within the active areas (ACT); bit line structures (BL) on the substrate (100) and connected to (‘connected to […] SD1’; Paragraph [0033]’) the first source/drain regions (SD1); and information storage portions (‘data storage element may be a capacitor’ (CA); Paragraph [0036]) on the substrate (100) and connected to (‘connected to […] SD2’; Paragraph [0036]) the second source/drain regions (SD2).
Regarding Claim 13, Jeon teaches a semiconductor memory device (‘semiconductor memory device’; Figs. 1 (plan-view) and 4 (cross-section), Paragraph [0006]), comprising: (Note: Referenced paragraphs may refer to figure 2A when referring to features identical between the embodiments of figures 2A and 4)
a substrate (100) including an element separation film (‘device isolation layer’ (110); Paragraph [0019]) defining active areas (‘active regions’ (ACT); Paragraph [0019]); and
gate structures (Gate structure components (GL) and (210) are shown to be in the trench (120); Fig.4) in trenches (120) on the substrate (100), respectively, the gate structures intersecting (‘extend crossing the active regions (ACT); Fig.1, Paragraph [0020]) the active areas (ACT), and each of the gate structures including:
a gate insulating layer (‘gate dielectric layer’ (210); Fig. 4, Paragraph [0027]) extending along sidewalls and a bottom surface of a corresponding one of the trenches (120),
a gate electrode layer (Gate Line (GL) component (230) and (240) together) on the gate insulating layer (210), the gate electrode layer ((230) and (240) together) including a first metal layer (‘conductive layer’ (230); Paragraph [0021]) and a second metal layer (‘first work function adjusting layer’ (240); Paragraph [0021]) on the first metal layer (230),
a work function adjusting film (‘liner layer’ (220); Paragraph [0022]) between the gate insulating layer (210) and the gate electrode layer (Paragraphs [0022] & [0024]), and
a capping film (‘first capping layers’ (250); Paragraph [0029]) in contact with the second metal layer (240).
wherein a lower surface of the second metal layer (240) is in contact with an upper surface of the work function adjusting film (220) and an upper surface of the first metal layer (230), respectively (‘may have a bottom surface in contact with […] the top surfaces of the liner layer (220) and the conductive layer (230)’; Fig. 4, Paragraph [0046]),
wherein a step is defined between the upper surface of the work function adjusting film (220) and the upper surface of the first metal layer (230) (the upper surface of the liner layer (220) is a step height below, i.e. non-coplanar with, the conductive layer (230); Fig. 4, Paragraph [0047]).
Jeon does not explicitly teach wherein each of the first metal layer, the second metal layer, and the work function adjusting film includes molybdenum (Mo).
Jeon2010 teaches at least a semiconductor memory device (‘semiconductor device’ (2); Fig. 4, Paragraph [0039]) wherein each of the first metal layer (‘lower buried word line’ (250a); Paragraph [0040]) and the second metal layer (‘upper buried word line,’ (250b); Paragraph [0040]) includes molybdenum (Mo) (“materials for forming the word line 150 illustrated Figs. 2E and 2F may be used to form the lower buried word line 250a and the upper buried word line 250b,” Paragraph [0042]; “the word line 150 may include at least one of […] molybdenum (Mo),” Paragraph [0031]). (Note: Although Paragraph [0040] suggests the two word lines use made of different materials, Paragraph [0031] states that the word line includes at least one material and thus 250a and 250b could both include molybdenum while still using a different material).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Jeon2010 into the device of Jeon such that the semiconductor memory device has a first metal layer and second metal layer comprising molybdenum. This is because the resulting device would have improved efficiency and electrical properties from using a lower resistance material (Paragraph [0031]).
Jeon as modified by Jeon2010 does not explicitly teach wherein the work function adjusting film includes molybdenum (Mo).
Thombare teaches at least a semiconductor memory device (“DRAM architecture;” Figs. 2 (trench of DRAM structure), 1A (metallization stacks used in Fig. 2), Paragraphs [0022, 0023]) wherein the work function adjusting film (“conformal barrier layer,” (206); Fig. 2A, Paragraph [0028]) includes molybdenum (Mo) (“barrier layers including […] molybdenum carbon nitride;” Paragraph [0024]; Note: both 206 in Fig. 2 and 106 in Fig. 1A are barrier layers and are located at the same spot in the material stacks so are referring to the same material. Fig. 5 (a related method) also shows this).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Thombare into the device of Jeon as modified by Jeon2010 such that the work function adjusting film comprises molybdenum. This is because the structure of a molybdenum gate electrode and molybdenum liner film is a metallization stack with low resistance characteristics that can improve efficiency by being applied to a semiconductor device (Paragraph [0023, 0028]).
Regarding Claim 15, Jeon as modified by Jeon2010 and Thombare teaches the semiconductor memory device (Jeon, Fig. 4) as claimed in claim 13, wherein the upper surface of the first metal layer (230) is positioned at a higher level than the upper surface of the work function adjusting film ((220); Paragraph [0047]).
Regarding Claim 16, Jeon as modified by Jeon2010 and Thombare teaches the semiconductor memory device (Jeon, Fig. 4) as claimed in claim 13, wherein the second metal layer (240) includes a first area ((A1); Annotated Fig.4) in contact with the upper surface of the first metal layer (230) and a second area ((A2); Annotated Fig.4) in contact with the upper surface of the work function adjusting film (220), a first width ((W1); Annotated Fig.4) of the first area (A1) being smaller than a second width ((W2); Annotated Fig. 4) of the second area (A2).
An annotated section of Fig. 4 of Jeon is included below for reference.
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Jeon Fig. 4; Annotated
Regarding Claim 17, Jeon as modified by Jeon2010 and Thombare teaches the semiconductor memory device (Jeon, Fig. 4) as claimed in claim 13, wherein each of the first metal layer (230) and the second metal layer (240) includes at least one of W, TiN, and Ru (‘may include […] titanium nitride’; Paragraphs [0023] and [0025]).
Regarding Claim 20, Jeon teaches a semiconductor memory device (Figs. 1 (plan-view) and 2A (cross-section), Paragraph [0018]), comprising:
a substrate (100) including an element separation film (‘device isolation layer’ (110); Fig. 2A, Paragraph [0019]) defining active areas (‘active regions’ (ACT); Paragraph [0019]);
first and second source/drain regions ((SD1) and (SD2)) within the active areas (ACT);
bit line structures (BL) on the substrate (100) and connected to (‘connected to […] (SD1)’; Paragraph [0033]’) the first source/drain regions (SD1);
information storage portions (‘data storage element may be a capacitor’ (CA); Paragraph [0036]) on the substrate (100) and connected to (‘connected to […] (SD2)’; Paragraph [0036]) the second source/drain regions (SD2); and
gate structures (Gate structure components (GL) and (210) are shown to be in the trench ((120); Fig. 2A) in trenches (120) on the substrate (100), respectively, the gate structures intersecting (‘extend crossing the active regions (ACT); Fig.1, Paragraph [0020]) the active areas (ACT), and each of the gate structures including:
a gate insulating layer (‘gate dielectric layer’ (210); Fig. 2A, Paragraph [0027]) extending along sidewalls and a bottom surface of a corresponding one of the trenches (120),
a gate electrode layer (Gate Line (GL) component (230) and (240) together) on the gate insulating layer (210), the gate electrode layer ((230) and (240) together) including a first metal layer (‘conductive layer’ (230); Paragraph [0021]) and a second metal layer (‘first work function adjusting layer’ (240); Paragraph [0021]) on the first metal layer (230),
a liner film (‘liner layer’ (220); Paragraph [0021]) between the gate insulating layer (210) and the first metal layer (230), the liner film (220) including a same metal material (‘titanium nitride (TiN)’; Paragraph [0022]) as the first metal layer ((230); Paragraph [0023]) and the second metal layer ((240); Paragraph [0024]) and
a capping film (‘first capping layers’ (250); Paragraph [0029]) in contact with the second metal layer (240), and
wherein a lower surface of the second metal layer (240) is in contact with an upper surface of the liner film (220).
Jeon does not explicitly teach wherein each of the first metal layer, the second metal layer, and the liner film includes molybdenum (Mo).
Jeon2010 teaches at least a semiconductor memory device (‘semiconductor device’ (2); Fig. 4, Paragraph [0039]) wherein each of the first metal layer (‘lower buried word line’ (250a); Paragraph [0040]) and the second metal layer (‘upper buried word line,’ (250b); Paragraph [0040]) includes molybdenum (Mo) (“materials for forming the word line 150 illustrated Figs. 2E and 2F may be used to form the lower buried word line 250a and the upper buried word line 250b,” Paragraph [0042]; “the word line 150 may include at least one of […] molybdenum (Mo),” Paragraph [0031]). (Note: Although Paragraph [0040] suggests the two word lines use made of different materials, Paragraph [0031] states that the word line includes at least one material and thus 250a and 250b could both include molybdenum while still using a different material).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Jeon2010 into the device of Jeon such that the semiconductor memory device has a first metal layer and second metal layer comprising molybdenum. This is because the resulting device would have improved efficiency and electrical properties from using a lower resistance material (Paragraph [0031]).
Jeon as modified by Jeon2010 does not explicitly teach wherein the liner film includes molybdenum (Mo).
Thombare teaches at least a semiconductor memory device (“DRAM architecture;” Figs. 2 (trench of DRAM structure), 1A (metallization stacks used in Fig. 2), Paragraphs [0022, 0023]) wherein the liner film (“conformal barrier layer,” (206); Fig. 2A, Paragraph [0028]) includes molybdenum (Mo) (“barrier layers including […] molybdenum carbon nitride;” Paragraph [0024]; Note: both 206 in Fig. 2 and 106 in Fig. 1A are barrier layers and are located at the same spot in the material stacks so are referring to the same material. Fig. 5 (a related method) also shows this).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Thombare into the device of Jeon as modified by Jeon2010 such that the liner film comprises molybdenum. This is because the structure of a molybdenum gate electrode and molybdenum liner film is a metallization stack with low resistance characteristics that can improve efficiency by being applied to a semiconductor device (Paragraph [0023, 0028]).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Jeon2010 and Thombare, further in view of Kwon et al. (US Pub. 2021/0066466 A1), hereinafter Kwon.
Regarding Claim 7, Jeon as modified by Jeon2010 and Thombare teaches the semiconductor memory device (Jeon, Fig. 4, Paragraph [0018]) as claimed in claim 1,
Jeon as previously modified does not expressly teach the gate structures further including an oxide film between the first metal layer and the second metal layer.
Kwon teaches a semiconductor memory device (‘semiconductor device’ (500); Fig. 6, Paragraph [0071]) wherein each of the gate structures (500G) further includes an oxide film (‘second barrier layer’ (525); Paragraph [0072]) between the first metal layer (‘low resistance gate electrode’ (524); Paragraph [0072]) and the second metal layer (‘upper buried portion’ (522); Paragraph [0072]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Kwon into the device of Jeon such that an oxide barrier layer exists between the metal layers. The incorporation of the oxide barrier layer between the two metal layers would be motivated by the fact that doing so would prevent mutual diffusion and reaction between different materials (Kwon, Paragraph [0019]).
Regarding Claim 8, Jeon as modified by Jeon2010, Thombare, and Kwon further teaches the semiconductor memory device (Kwon, ‘semiconductor device’ (500); Fig. 6, Paragraph [0071]) as claimed in claim 7, wherein the oxide film (Kwon, (525)) includes a first area (Kwon, portion of (525) in contact with (523)) adjacent to the liner film (Kwon, ‘first barrier layer’ (523); Paragraph [0072]) and a second area (Kwon, portion of (525) in contact with (523)) adjacent to the first metal layer.
Claims 4, 14, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Jeon2010 and Thombare, further in view of Lee et al. (US Pub. 2008/0211057), hereinafter Lee.
Regarding Claim 4, Jeon as modified by Jeon2010 and Thombare teaches the semiconductor memory device (‘semiconductor memory device’; Figs. 4, Paragraph [0006]), as claimed in claim 1,
Jeon does not expressly teach that a height of an upper surface of the liner film is higher than a height of an upper surface of the first metal layer.
Lee teaches a semiconductor memory device (‘semiconductor device’ (100); Fig. 4, Paragraph [0075]), wherein a height of an upper surface of the liner film (‘gate electrode layer’ (130); Paragraph [0076]) is higher than a height of an upper surface of the first metal layer (‘lower buried word line’ (150); Paragraph [0076]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lee into the device of Jeon such that the semiconductor memory device has a height of an upper surface of the liner film higher than a height of an upper surface of the first metal layer. This would be motivated by the fact that a higher height of the liner film (covering the sides of both metal layers) would provide the benefit of allowing the capping film to simultaneously cap the recessed region of the second metal layer and liner film (Lee, Paragraph [0070]).
Regarding Claim 14, Jeon as modified by Jeon2010 and Thombare teaches the semiconductor memory device (Fig. 4, Paragraph [0018]) as claimed in claim 13,
Jeon does not expressly teach that the upper surface of the work function adjusting film is positioned at a higher level than the upper surface of the first metal layer.
Lee teaches a semiconductor memory device (‘semiconductor device’ (100); Fig. 4, Paragraph [0075]),
wherein the upper surface of the work function adjusting film (‘gate electrode layer’ (140); Paragraph [0076]) is positioned at a higher level than the upper surface of the first metal layer (‘lower buried word line’ (150); Paragraph [0076]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lee into the device of Jeon such that the semiconductor memory device has a height of an upper surface of the work function adjusting film higher than a height of an upper surface of the first metal layer. This would be motivated by the fact that a higher height of the work function adjusting film (covering the sides of both metal layers) would provide the benefit of allowing the capping film to simultaneously cap the recessed region of the second metal layer and liner film (Lee, Paragraph [0070]).
Regarding Claim 18, Jeon as modified by Jeon2010 and Thombare teaches the semiconductor memory device (Fig. 4, Paragraph [0018]) as claimed in claim 17,
Jeon does not expressly teach that the work function adjusting film includes any of LaO, ScO, AlO, MgO, HfO2, Y203, Ta, TaN, and TiSiN.
Lee teaches a semiconductor memory device (‘semiconductor device’ (100); Fig. 4, Paragraph [0075]), wherein the work function adjusting film (‘gate electrode layer’ (130); Paragraph [0079]) includes any of LaO, ScO, AlO, MgO, HfO2, Y203, Ta, TaN, and TiSiN (‘titanium silicon nitride (TiSiN)’; Paragraph [0079]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lee into the device of Jeon by substituting the nitride material (TiN) in the work function adjusting film of Jeon with TiSiN in Lee. This would be due to the fact that doing so would produce the expected result of maintaining the work function adjustment film’s resistivity below a desired value (Lee; Paragraph [0074]).
Regarding Claim 19, Jeon as modified by Jeon2010 and Thombare and further modified by Lee further teaches the semiconductor memory device (Lee, (100)) as claimed in claim 18, wherein
the work function adjusting film (Lee, (130)) includes a compound of any of the LaO, ScO, AlO, MgO, HfO2, Y2O3, Ta, TaN, and TiSiN (Lee, ‘(TiSiN)’; Paragraph [0041]), and at least one of the W, TiN, and Ru (Lee, ‘may include […] (TiN) […] or a combination thereof’; Paragraph [0041]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nolan Stuessy whose telephone number is (571) 645-5843. The examiner can normally be reached weekdays 7:30 - 17:00 US Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NOLAN GABRIEL STUESSY/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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