DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/13/2023 and 02/21/2025 are being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 and 9 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Huang et al. (US 2022/0352326 A1)
Regarding claim 1, Huang et al. teaches a semiconductor structure (FIG. 25, oriented upside down), comprising:
a transistor (drain feature 232D, source feature 232S, channel layers 208, gate dielectric layer 212’, gate electrode layer 213’) at a first side of the semiconductor structure (layers above 260);
a contact (backside source contact 268) to the transistor at a second side of the semiconductor structure (layer 260); and
sidewall spacers (barrier layer 264 or dielectric layer 260) surrounding a portion of sidewalls of the contact;
wherein the contact has a first width (268 protruding into 232S) above the sidewall spacers and a second width (268 at interface with 270) below the sidewall spacers, the second width being different than the first width.
Regarding claim 2, Huang et al. teaches the semiconductor structure of claim 1, wherein the second width (268 at interface with 270) is greater than (FIG. 25, oriented upside down) the first width (268 protruding into 232S).
Regarding claim 3, Huang et al. teaches the semiconductor structure of claim 1, wherein the contact (backside source contact 268) has a third width (width between second width 268 at interface with 270 and first width 268 protruding into 232S) between upper and lower surfaces of the sidewall spacers (dielectric layer 260), the third width being different (FIG. 25, oriented upside down) than the first width (268 protruding into 232S) and the second width (268 at interface with 270).
Regarding claim 4, Huang et al. teaches the semiconductor structure of claim 3, wherein the first width (268 protruding into 232S) is greater (FIG. 25, oriented upside down) than the third width (width between second width 268 at interface with 270 and first width 268 protruding into 232S), and
wherein the second width (268 at interface with 270) is greater (FIG. 25, oriented upside down) than the first width (268 protruding into 232S).
Regarding claim 5, Huang et al teaches the semiconductor structure of claim 1, wherein the contact (backside source contact 268) connects to a source/drain region (source and drain features 232S/D) of the transistor (drain feature 232D, source feature 232S, channel layers 208, gate dielectric layer 212’, gate electrode layer 213’).
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FIG. 25 (above), oriented upside down and annotated
Regarding claim 9, Huang et al. teaches a semiconductor structure (FIG. 25, upright), comprising:
a transistor (combination of channel layers 208 and source and drain features 232S/D) at a first side (area between the lower surface of dielectric layer 260 and upper layer of gate dielectric layer 212′) of the semiconductor structure;
a placeholder (dielectric plug 246) self-aligned to a source/drain region (source feature 232S) of the transistor at a second side (area between the upper surface of gate dielectric layer 212′ and upper surface of second ILD layer 250) of the semiconductor structure; and
sidewall spacers (first ILD layer 238) surrounding a portion of sidewalls of the placeholder (246);
wherein the placeholder (246) has a first width (lower end of the concave of 246, just above upper surface of 238) above an upper surface of the sidewall spacers (238) and a second width (any width of 246 below upper layer of layer 238) below the upper surface of the sidewall spacers (238), the second width being different than the first width (FIG. 25).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-8, and 10-21 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2022/0352326 A1) in view of Wang et al. (US 2021/0082803 A1).
Regarding claim 1, Huang et al. teaches A semiconductor structure (FIG. 25), comprising:
a transistor (combination of channel layers 208 and source and drain features 232S/D) at a first side (area between the lower surface of dielectric layer 260 and upper layer of gate dielectric layer 212′) of the semiconductor structure; and
a contact (drain contact 248) to the transistor at a second side (area between the upper surface of gate dielectric layer 212′ and upper surface of second ILD layer 250) of the semiconductor structure.
Huang et al. is silent to sidewall spacers surrounding a portion of sidewalls of the contact; wherein the contact has a first width above the sidewall spacers and a second width below the sidewall spacers, the second width being different than the first width.
However, Wang et al. teaches sidewall spacers (Fig. 14, patterned barrier layer 214’) surrounding a portion of sidewalls of the contact (combination of conductive feature 224 and contact via 212);
wherein the contact has a first width (layer of 212 above upper surface of 214’ in the orientation where Fig. 14 is reflected in origin to match the plane which FIG. 25 is in) above the sidewall spacers (214’) and a second width (layer of 224 below lower surface of 214’) below the sidewall spacers (214’), the second width being different than the first width (Fig. 14).
It would have been obvious to one of ordinary skill in the art before the effective filing date, to use the patterned barrier layer 214’ of Fig. 14 in Wang et al. in place of the bottom interlayer dielectric (ILD) layer 236 of FIG. 25 of Huang et al. as the sidewall spacers surrounding portions of contact. Using a sidewall spacer with both upper and lower surfaces isolated from bordering another feature to the contact, as shown in Fig. 14 of Wang et al., in combination with the rest of the semiconductor structure taught by Huang et al. in FIG. 25, would enable size reduction of structural features, specifically of the sidewall spacers, allowing for increased performance at lower power and cost ([0001]).
Regarding claim 2, Huang et al. in view of Wang et al. teaches the semiconductor structure of claim 1. Wang et al. teaches wherein the second width (Fig. 14 in orientation reflected in origin: layer of 224 below lower surface of 214’) is greater than the first width (layer of 212 above upper surface of 214’).
The contact (248) in FIG. 25 of Huang et al. has sidewall spacers oriented such that only the width above the spacers is exposed. The lower surface of the contact (248) is additionally longer than the upper surface. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor structure of FIG. 25 in Huang et al. with spacers (214’) as taught by Wang et al. in Fig. 14 such that both upper and lower surfaces of the contact are free from sharing a surface with the spacers, and the longer lower surface width and shorter upper surface width is exposed.
Regarding claim 3, Huang et al. in view of Wang et al. teaches the semiconductor structure of claim 1. Wang et al. teaches wherein the contact (Fig. 14, combination of conductive feature 224 and contact via 212) has a third width (any width in 212 between upper and lower surfaces of 214’) between upper and lower surfaces of the sidewall spacers (patterned barrier layer 214’), the third width being different (Fig. 14) than the first width and the second width.
The contact (248) taught in FIG. 25 of Huang et al. tapers out to a longer bottom surface width with the midsection width of the contact being of a different length than the upper and lower surfaces. To expose the lower surface of the contact below the spacers to create an lower surface below the sidewall spacers’ lower surface, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified contact (248) and sidewall spacers (236) of FIG. 25 in Huang et al. with the contact (212 + 224) and spacers (214’) in Fig. 14 of Wang et al. to create a width of another length in the contact between the isolated spacers’ upper and lower surfaces.
Regarding claim 5, Huang et al. in view of Wang et al. teaches the semiconductor structure of claim 1. Huang et al. teaches wherein the contact (FIG. 25, drain contact 248) connects to a source/drain region (source feature 232D) of the transistor.
Regarding claim 6, Huang et al. in view of Wang et al. teaches the semiconductor structure of claim 5. Huang et al. teaches further comprising:
a placeholder (FIG. 25, dielectric plug 246) at the second side (area between the upper surface of gate dielectric layer 212′ and upper surface of second ILD layer 250) of the semiconductor structure directly below another source/drain region (drain feature 232S) of the transistor; and
additional sidewall spacers (first ILD layer 238) surrounding a portion of sidewalls of the placeholder;
wherein the placeholder (246) has a third width (lower end of the concave of 246, just above upper surface of 238) above an upper surface of the additional sidewall spacers (238) and a fourth width (any width of 246 below upper layer of layer 238) below the upper surface of the additional sidewall spacers (238), the third width being different than the fourth width (FIG. 25).
Regarding claim 7, Huang et al. in view of Wang et al. teaches the semiconductor structure of claim 6. Huang et al. teaches wherein the fourth width (any width of 246 below upper layer of layer 238) is greater than the third width (lower end of the concave of 246, just above upper surface of 238).
Regarding claim 8, Huang et al. in view of Wang et al. teaches the semiconductor structure of claim 6. Huang et al. teaches wherein the additional sidewall spacers (FIG. 25, first ILD layer 238) surrounding the portion of the sidewalls of the placeholder (246) are vertically aligned (FIG. 25) surrounding the portion of the sidewalls of the contact (bottom interlayer dielectric (ILD) layer 236).
Regarding claim 10, Huang et al. in view of Wang et al. teaches the semiconductor structure of claim 9. Huang et al. teaches wherein the second width (FIG.25, any width of 246 below upper layer of layer 238) is greater than the first width (lower end of the concave of 246, just above upper surface of 238).
Regarding claim 11, Huang et al. in view of Wang et al. teaches the semiconductor structure of claim 9. Huang et al. teaches further comprising:
a contact (FIG. 25, drain contact 248) to another source/drain region (drain feature 232D) of the transistor at the second side (area between the upper surface of gate dielectric layer 212′ and upper surface of second ILD layer 250) of the semiconductor structure.
Huang et al. is silent to additional sidewall spacers surrounding a portion of sidewalls of the contact; wherein the contact has a third width above the additional sidewall spacers and a fourth width below the additional sidewall spacers, the third width being different than the fourth width.
However, Wang et al. teaches additional sidewall spacers (Fig. 14, patterned barrier layer 214’) surrounding a portion of sidewalls of the contact (combination of conductive feature 224 and contact via 212);
wherein the contact (combination of conductive feature 224 and contact via 212) has a third width (layer of 212 above upper surface of 214’ in the orientation where Fig. 14 is reflected in origin to match the plane which FIG. 25 is in) above the additional sidewall spacers and a fourth width (layer of 224 below lower surface of 214’) below the additional sidewall spacers, the third width being different than the fourth width (Fig. 14).
It would have been obvious to one of ordinary skill in the art before the effective filing date, to use the patterned barrier layer 214’ of Fig. 14 in Wang et al. in place of the bottom interlayer dielectric (ILD) layer 236 of FIG. 25 of Huang et al. as the sidewall spacers surrounding portions of contact. Using a sidewall spacer with both upper and lower surfaces isolated from bordering another feature to the contact, as shown in Fig. 14 of Wang et al., in combination with the rest of the semiconductor structure taught by Huang et al. in FIG. 25, would enable size reduction of structural features, allowing for increased performance at lower power and cost ([0001]).
Regarding claim 12, Huang et al. in view of Wang et al. teaches the semiconductor structure of claim 11. Wang et al. teaches wherein the fourth width (layer of 224 below lower surface of 214’ in the orientation where Fig. 14 is reflected in origin to match the plane which FIG. 25 is in) is greater (Fig. 14) than the third width (layer of 212 above upper surface of 214’).
The contact (248) in FIG. 25 of Huang et al. has sidewall spacers oriented such that only the width above the spacers is exposed. The lower surface of the contact (248) is additionally longer than the upper surface. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor structure of FIG. 25 in Huang et al. with spacers (214’) as taught by Wang et al. in Fig. 14 such that both upper and lower surfaces of the contact are free from sharing a surface with the spacers, and the longer lower surface width and shorter upper surface width is exposed.
Regarding claim 13, Huang et al. teaches a semiconductor structure (FIG. 25), comprising:
a transistor (combination of channel layers 208 and source and drain features 232S/D) disposed at a first side (area between the lower surface of dielectric layer 260 and upper layer of gate dielectric layer 212’) of the semiconductor structure;
a placeholder (dielectric plug 246) at a second side (area between the upper surface of gate dielectric layer 212′ and upper surface of second ILD layer 250) of the semiconductor structure, the placeholder being self-aligned to a first source/drain region (drain feature 232S) of the transistor;
a contact (drain contact 248) to a second source/drain region (source feature 232D) of the transistor at the second side (area between the upper surface of gate dielectric layer 212′ and upper surface of second ILD layer 250) of the semiconductor structure; and
sidewall spacers (first ILD layer 238) surrounding portions of sidewalls of the placeholder (246) and the contact (248);
wherein a first portion (lower end of the concave of 246, just above upper surface of 238) of the placeholder (246) above an upper surface of the sidewall spacers has a different width (FIG. 25) than a second portion (any width of 246 below upper surface of 238) of the placeholder (246) below the upper surface of the sidewall spacers;
Huang et al. is silent to wherein a first portion of the contact above the upper surface of the sidewall spacers has a different width than a second portion of the contact below a lower surface of the sidewall spacers.
However, Wang et al. teaches wherein a first portion (layer of 212 above upper surface of 214’ in the orientation where Fig. 14 is reflected in origin to match the plane which FIG. 25 is in) of the contact (combination of conductive feature 224 and contact via 212) above the upper surface of the sidewall spacers has a different width (Fig. 14) than a second portion (layer of 224 below lower surface of 214’) of the contact (224 + 212) below a lower surface of the sidewall spacers.
It would have been obvious to one of ordinary skill in the art before the effective filing date, to use the contact (combination of conductive feature 224 and contact via 212) and its sidewalls (patterned barrier layer 214’) exposing both upper and lower surfaces as in Fig. 14 of Wang et al in place of the contact (drain contact 248) and its sidewall (bottom interlayer dielectric (ILD) layer 236) exposing only the lower surface from FIG. 25 of Huang et al. Using a contact that exposes portions exposed both above and below the sidewall spacers calls for a reduction in sidewall spacers size, resulting in miniaturization and thus increased performance at lower power and cost ([0001]).
Regarding claim 14, Huang et al. in view of Wang et al. teaches the semiconductor structure of claim 13. Huang et al. teaches wherein the first portion (FIG. 25, lower end of the concave of 246, just above upper surface of 238) of the placeholder above the upper surface of the sidewall spacers has a smaller width (FIG. 25) than the second portion (any width of 246 below upper surface of 238) of the placeholder below the upper surface of the sidewall spacers.
Regarding claim 15, Huang et al. in view of Wang et al. teaches the semiconductor structure of claim 13. Wang et al. teaches wherein the first portion (layer of 212 above upper surface of 214’ in the orientation where Fig. 14 is reflected in origin to match the plane which FIG. 25 is in) of the contact above the upper surface of the sidewall spacers has a smaller width (Fig. 14) than the second portion (layer of 224 below lower surface of 214’) of the contact below the lower surface of the sidewall spacers.
The contact (248) in FIG. 25 of Huang et al. has sidewall spacers oriented such that only the width above the spacers is exposed. The upper surface of the contact (248) is additionally shorter than the lower surface. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor structure of FIG. 25 in Huang et al. with spacers (214’) as taught by Wang et al. in Fig. 14 such that both upper and lower surfaces of the contact are free from sharing a surface with the spacers, and the longer lower surface width and shorter upper surface width is exposed.
Regarding claim 16, Huang et al. in view of Wang et al. teaches the semiconductor structure of claim 15. Wang et al. teaches wherein a third portion (width in area of 212 between upper and lower surfaces of 214’ in the orientation where Fig. 14 is reflected in origin to match the plane which FIG. 25 is in) of the contact between the upper and lower surfaces of the sidewall spacers has a different width (Fig. 14) than the first portion (area of 212 above upper surface of 214’ of the contact above the upper surface of the sidewall spacers) and the second portion (area of 224 below lower surface of 214’) of the contact below the lower surface of the sidewall spacers.
The contact (248) taught in FIG. 25 of Huang et al. tapers out to a longer bottom surface width with the midsection width of the contact being of a different length than the upper and lower surfaces. To expose the lower surface of the contact below the spacers to create a lower surface below the sidewall spacers’ lower surface, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified contact (248) and sidewall spacers (236) of FIG. 25 in Huang et al. with the contact (212 + 224) and spacers (214’) in Fig. 14 of Wang et al. to create a width of another length in the contact between the isolated spacers’ upper and lower surfaces.
Regarding claim 17, Huang et al. in view of Wang et al. teaches the semiconductor structure of claim 13. Wang et al. teaches wherein the upper surface of the sidewall spacers (Fig. 14, barrier layer 214’) is separated from a bottom dielectric insulator layer ([0020], metal etch stop layer (MESL) 206 formed of a dielectric material) of the transistor by an interlayer dielectric layer (first dielectric layer 208).
The contact (248) in FIG. 25 of Huang et al. does not have an exposed upper surface above the upper surface of the sidewall spacers. Furthermore, the bottom ILD layer (236) is directly above the sidewall spacer (238). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor structure of Huang et al. in FIG. 25 to include the interlayer dielectric layer (208) of Fig, 14 in Wang et al. in between the spacers (238) and bottom dielectric insulator layer (236) of FIG. 25 in Huang et al.
Regarding claim 18, Huang et al. teaches a transistor structure (FIG. 25, combination of channel layers 208 and source and drain features 232S/D), comprising:
a first source/drain region (source feature 232S);
a second source/drain region (drain feature 232D);
a placeholder (dielectric plug 246) self-aligned to a backside of the first source/drain region (source feature 232S);
a contact (drain contact 248) connected to a backside of the second source/drain region (drain feature 232D); and
sidewall spacers (first ILD layer 238) surrounding portions of sidewalls of the placeholder (246) and the contact (248);
wherein a first portion (lower end of the concave of 246, just above upper surface of 238) of the placeholder (246) above an upper surface of the sidewall spacers has a different width (FIG. 25) than a second width (any width of 246 below upper surface of 238) of the placeholder below the upper surface of the sidewall spacers;
Huang et al. is silent to wherein a first portion of the contact above the upper surface of the sidewall spacers has a different width than a second portion of the contact below a lower surface of the sidewall spacers.
However, Wang et al. teaches wherein a first portion (layer of 212 above upper surface of 214’ in the orientation where Fig. 14 is reflected in origin to match the plane which FIG. 25 is in) of the contact (248) above the upper surface of the sidewall spacers has a different width (Fig. 14) than a second portion (layer of 224 below lower surface of 214’) of the contact below a lower surface of the sidewall spacers.
It would have been obvious to one of ordinary skill in the art before the effective filing date, to use the contact (combination of conductive feature 224 and contact via 212) and its sidewalls (patterned barrier layer 214’) exposing both upper and lower surfaces as in Fig. 14 of Wang et al in place of the contact (drain contact 248) and its sidewall (bottom interlayer dielectric (ILD) layer 236) exposing only the lower surface from FIG. 25 of Huang et al. Using a contact that exposes portions exposed both above and below the sidewall spacers calls for a reduction in sidewall spacers size, resulting in miniaturization and thus increased performance at lower power and cost ([0001]).
Regarding claim 19, Huang et al. in view of Wang et al. teaches the transistor structure of claim 18. Huang et al. teaches wherein the first portion (FIG. 25, lower end of the concave of 246, just above upper surface of 238) of the placeholder (246) above the upper surface of the sidewall spacers has a smaller width (FIG. 25) than the second portion (any width of 246 below upper surface of 238) of the placeholder below the upper surface of the sidewall spacers.
Regarding claim 20, Huang et al. in view of Wang et al. teaches the transistor structure of claim 18. Wang et al. teaches wherein the first portion (layer of 212 above upper surface of 214’ in the orientation where Fig. 14 is reflected in origin to match the plane which FIG. 25 is in) of the contact (224 + 212) above the upper surface of the sidewall spacers has a smaller width (Fig. 14) than the second portion (layer of 224 below lower surface of 214’) of the contact below the lower surface of the sidewall spacers.
The contact (248) in FIG. 25 of Huang et al. has sidewall spacers oriented such that only the width above the spacers is exposed. The upper surface of the contact (248) is additionally shorter than the lower surface. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor structure of FIG. 25 in Huang et al. with spacers (214’) as taught by Wang et al. in Fig. 14 such that both upper and lower surfaces of the contact are free from sharing a surface with the spacers, and the longer lower surface width and shorter upper surface width is exposed.
Regarding claim 21, Huang et al. in view of Wang et al. teaches the transistor structure of claim 18. Wang et al. teaches wherein the upper surface (Fig. 14, barrier layer 214’) of the sidewall spacers is separated from a bottom dielectric insulator layer ([0020], metal etch stop layer (MESL) 206 formed of a dielectric material) of the transistor structure by an interlayer dielectric layer (first dielectric layer 208).
The bottom ILD layer (236) in FIG. 25 of Huang et al. is directly above the sidewall spacer (238). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor structure of Huang et al. in FIG. 25 to also include an interlayer dielectric layer (208) of Fig, 14 in Wang et al. in between the spacers (238) and bottom dielectric insulator layer (236) of FIG. 25 in Huang et al.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. in view of Wang et al. and Chang et al. (US 2023/0026310 A1).
Regarding claim 4, Huang et al. in view of Wang et al. teaches the semiconductor structure of claim 3. Wang et al. teaches wherein the second width (Fig. 14 in orientation reflected in origin: layer of 224 below lower surface of 214’) is greater than the first width (layer of 212 above upper surface of 214’) but fails to teach further wherein the first width is greater than the third width.
However, Chang et al. teaches further wherein the first width (FIG. 2V-1, upper surface of contact plug 190) is greater than the third width (innermost surface width in concave of 190).
Chang et al. is considered analogous art because it is reasonably pertinent to the field of semiconductor structures, in which contact and sidewall spacers are present. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor structure as taught by the combination of Huang et al. in view of Wang et al. to incorporate the contact (190) in FIG. 2V-1 as taught in Chang et al.
Claim 22-25 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. in view of Wang et al. and Park et al. (US 2015/0028494A1).
Regarding claim 22, Huang et al. in view of Wang et al. teaches the semiconductor structure in claim 1 but fails to teach further an integrated circuit comprising the semiconductor structure in claim 1.
However, Park et al. teaches an integrated circuit (FIG. 3, integrated circuit device 10C) comprising the semiconductor structure in claim 1.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have implemented the semiconductor structure as taught by the combination of Huang et al. in view of Wang et al. to the integrated circuit device as taught in Park et al. because the IC device provided includes a through-silicon-via (TSV) structure ([0053]), which is a semiconductor device.
Regarding claim 23, Huang et al. in view of Wang et al. and Park et al. teaches the integrated circuit in claim 22. Wang et al. teaches wherein the second width (Fig. 14 in orientation reflected in origin: layer of 224 below lower surface of 214’) is greater than the first width (layer of 212 above upper surface of 214’).
The contact (248) in FIG. 25 of Huang et al. has sidewall spacers oriented such that only the width above the spacers is exposed. The lower surface of the contact (248) is additionally longer than the upper surface. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor structure of FIG. 25 in Huang et al. with spacers (214’) as taught by Wang et al. in Fig. 14 such that both upper and lower surfaces of the contact are free from sharing a surface with the spacers, and the longer lower surface width and shorter upper surface width is exposed.
Regarding claim 24, Huang et al. in view of Wang et al. and Park et al. teaches the integrated circuit in claim 22. Huang et al. teaches wherein the contact (drain contact 248) connects to a source/drain region (drain feature 232D) of the transistor.
Regarding claim 25, Huang et al. in view of Wang et al. and Park et al. teaches the integrated circuit in claim 24. Huang et al. teaches wherein the semiconductor structure (FIG. 25) further comprises
placeholder (dielectric plug 246) at the second side (area between the upper layer of gate dielectric layer 212′ and upper layer of second ILD layer 250) of the semiconductor structure directly below another source/drain region (source feature 232S) of the transistor and
additional sidewall spacers (first ILD layer 238) surrounding a portion of sidewalls of the placeholder (dielectric plug 246), and
wherein the placeholder (246) has a third width (lower end of the concave of 246, just above upper surface of 238) above an upper surface of the additional sidewall spacers and a fourth width (any width of 246 below upper surface of 238) below the upper surface of the additional sidewall spacers, the third width being different (FIG. 25) than the fourth width.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEANNE M KIM whose telephone number is (571)272-8768. The examiner can normally be reached Monday-Thursday 8:00-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JEANNE MYON KIM/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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