Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-9 in the reply filed on June 23, 2026 is
acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/13/2023 and 06/09/2023 is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 8 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Ko et al. (KR 20200008342 A).
Regarding claim 1, Ko et al. teaches a semiconductor chip (first semiconductor device C1) comprising:
a semiconductor substrate (second semiconductor substrate 151) having an active surface (lower surface 156) and an inactive surface (upper surface 155) opposite (FIG. 2a) the active surface;
a semiconductor device layer (second semiconductor device layer 152) disposed on (FIG. 1) the active surface (lower surface 156); and
a modified region (modification region A) positioned on an entirety of a lateral side surface ([0081], side surface of semiconductor device C exposed to outside) of the semiconductor substrate (second semiconductor substrate 151).
Regarding claim 2, Ko et al. teaches the semiconductor chip of claim 1, wherein the modified region (modification region A) comprises a region (edges D1 and D2) that the semiconductor substrate (second semiconductor substrate 151) is modified by laser (stealth laser device) as the semiconductor substrate is cut in a vertical direction ([0043], laser light pass through semiconductor substrate) by laser grooving ([0043], nonlinear multi-photon absorption and thermal melting).
Regarding claim 3, Ko et al. teaches the semiconductor chip of claim 1, wherein the modified region (modification region A) has a lower density than all other regions (([0041], less than density of inside center of semiconductor device C1) of the semiconductor substrate (second semiconductor substrate 151).
Regarding claim 4, Ko et al. teaches the modified region (modification region A) is amorphous ([0041]).
Regarding claim 8, Ko et al. teaches the semiconductor chip of claim 1, further comprising:
a first through electrode (second through electrode 153) passing through (FIG. 1) the semiconductor substrate (second semiconductor substrate 151) in a vertical direction (direction perpendicular to width of semiconductor package 100);
a first connection pad (second connection pad 154) disposed on (FIG. 1) the inactive surface (upper surface 155) and electrically connected (FIG. 1) to the first through electrode (second through electrode 153); and
a passivation layer ([0030], electrical patterning layer) disposed on ([0030]) the inactive surface (upper surface 155).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Ko et al. (KR 20200008342 A) in view of Vinciguerra et al. (US 20120329213 A1).
Regarding claim 5, Ko et al. teaches the semiconductor chip of claim 1. Vinciguerra et al. teaches wherein a sum of vertical lengths (total thickness T5) of the semiconductor substrate (thickness T2 of flexible substrate 210) and the semiconductor device layer (FIG. 6, thickness T4 of 220a) is less than or equal to 20 μm ([0080], range 15-150 micrometers, which contains limitation of 20 μm or less).
It would have been obvious to someone of ordinary skill in the art before the effective filing date
of the claimed invention to have reduced the total thickness of semiconductor substrate and semiconductor device layer combined in Ko et al. to fit a range between 15 μm and 150 μm as taught in the flexible electrical device by Vinciguerra et al. A thick wafer is more prone to brittle fracture when cut due to higher mechanical stress. Using thinner wafers improves flexibility and reduces stress while maintaining function, thereby reducing damage during dicing and improving cutting accuracy and packaging behavior.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Ko et al. (KR 20200008342 A) in view of Kumazawa (US 11373907 B2).
Regarding claim 6, Ko et al. teaches the semiconductor chip of claim 1. Kumazawa teaches wherein a horizontal cross-sectional area (cross section of substrate 2 bounded laterally by inclined surfaces 12) of the semiconductor substrate (substrate 2) varies (FIG. 17 and 18, reproduced and annotated below: sides of substrate 2 widening) as a vertical level (height of thickness 100) of the semiconductor substrate increases (upwards direction from devices 5).
It would have been obvious to someone of ordinary skill in the art before the effective filing date
of the claimed invention to have modified the substrate of Ko et al. to have its horizontal cross-sectional area vary and more specifically increase towards the top, as taught by Kumazawa. Expanding the cross-sectional area can accommodate larger vias and interposer structures, which can help reduce the risk of via resistance and improve mechanical stability and performance at high density (bump) interconnects.
Regarding claim 7, Ko et al. in view of Kumazawa teaches the semiconductor chip of claim 6. Kumazawa teaches wherein a horizontal cross-sectional area (cross section of substrate 2 bounded laterally by inclined surfaces 12) of the semiconductor substrate (substrate 2) increases (FIG. 17 and 18, reproduced and annotated below: sides of substrate 2 widening) as a distance from the semiconductor device layer (devices 5) increases in a vertical direction (longitudinal direction along height of thickness 100).
It would have been obvious to someone of ordinary skill in the art before the effective filing date
of the claimed invention to have modified the substrate of Ko et al. to have its horizontal cross-sectional area gradually increase towards the top, as taught by Kumazawa. Expanding the cross-sectional area can accommodate larger vias and interposer structures, which can help reduce the risk of via resistance and improve mechanical stability and performance at high density (bump) interconnects.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Ko et al. (KR 20200008342 A) in view of Vinciguerra et al. (US 20120329213 A1) and Kumazawa (US 11373907 B2).
Regarding claim 9, Ko et al. teaches the semiconductor chip of claim 8. Ko et al. does not teach wherein: a horizontal cross-sectional area of the semiconductor substrate increases as a distance from the semiconductor device layer increases in the vertical direction; and a sum of vertical lengths of the semiconductor substrate and the semiconductor device layer is less than or equal to 20 pm.
However, Kumazawa teaches wherein a horizontal cross-sectional area (cross section of substrate 2 bounded laterally by inclined surfaces 12) of the semiconductor substrate (substrate 2) increases (FIG. 17 and 18, reproduced and annotated below: sides of substrate 2 widening) as a distance from the semiconductor device layer (devices 5) increases in the vertical direction.
Kumazawa does not teach wherein a sum of vertical lengths of the semiconductor substrate and the semiconductor device layer is less than or equal to 20 pm.
However, Vinciguerra et al. teaches wherein a sum of vertical lengths (total thickness T5) of the semiconductor substrate (thickness T2 of flexible substrate 210) and the semiconductor device layer (FIG. 6, thickness T4 of 220a) is less than or equal to 20 μm ([0080], range 15-150 micrometers, which contains limitation of 20 μm or less).
It would have been obvious to someone of ordinary skill in the art before the effective filing date
of the claimed invention to have reduced the chip thickness of device in Ko et al. to one in the range taught in Vinciguerra et al., and to have also modified the substrate of Ko et al. to have its horizontal cross section gradually increase in the vertical upwards direction. Thinner substrates, with their flexibility and reduced stress concentrations, enable higher integration density and thus an increased yield of semiconductor devices and packages. Wider horizontal cross sections of substrates are easier to cut without damage and with more accuracy due to greater mechanical stability, thus similarly improving yield for thin wafers and packaged chip stacks.
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FIG. 18 of Kumazawa: oriented upside down, depicting horizontal cross-section through substrate 2, with sides widening as distance from device 5 (see FIG. 17, not shown) on active surface (4) increases in the vertical direction pointed upwards.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEANNE M KIM whose telephone number is (571)272-8768. The examiner can normally be reached Monday-Thursday 8:00-6:00.
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/JEANNE MYON KIM/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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