DETAILED ACTION Priority Acknowledgment is made of applicant's claim for foreign priority based on an application filed in France on Dec. 14, 2022 . It is noted, however, that applicant has not filed a certified copy of the FR2213369 application as required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 12/13/2023 has been considered by the examiner. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites “…neighboring or adjacent quantum dots…”, which is unclear. It appears that “neighboring” and “adjacent” are synonyms; that is, two words describing a single limitation, rather than two separate options. Claim 3 recites “… wherein said second region of said semiconductor block forms a second quantum dot …”, which appears to already be required by claim 2 from which claim 3 depends. Claim 4 contains t he term “ near ” which is a relative term which renders the claim indefinite. The term “ near ” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Furthermore, claim 4 contains and opening parenthesis without a closing parenthesis. It is unclear if the single parenthesis a typographical error or if there is intended to be a portion of the claim within parentheses. Furthermore, claim 4 contains the word “ lower ” within quotation marks, which renders the claim indefinite as it is unclear why this term is in quotation marks. Claim 10 recites “a substrate”; however, “a substrate” is recited in claim 1 from which claim 10 depends. It appears that the “substrate” of claim 1 and claim 10 are referring to the same substrate and claim 10 is intending to further limit said substrate of claim 1. The claim will be interpreted with this assumption. Claim 11 recites the phrase “…advantageously provided…” which renders the claim indefinite as it is unclear what this phrase is supposed to mean. The examiner suggests removing the word “advantageously” from the claim. For the purposes of examination, this term will not be given any weight; that is, essentially ignored. Claims 12-15 are currently dependent upon claim 1; however, several of the elements are introduced multiple times. For example, “…manufacturing a quantum device according to claim 1…” appears to be intended to be “…manufacturing the quantum device according to claim 1…” (emphasis added). For example, “…and insulation zones…” appears to be intended to be “… said insulation zones…” (emphasis added). There are several similar issues throughout claims 12-15. In addition, claim 12 recites “gate blocks” which appears to mean the same thing as “front gates” from claim 1. Appropriate correction is required. The Examiner suggests Applicant consider decoupl ing claims 12-15 from claim 1; that is, to make claim 12 an independent claim. Whether Applicant chooses to keep claims 12-15 dependent upon claim 1 or to modify claim 12 into an independent claim, numerous adjustments will need to be made to these claims in order to overcome indefinite issues currently afflicting these claims. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-12 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bedecarrats et al. (IDS NPL Reference number 3); hereafter referred to as NPL3. Regarding independent claim 1 , NPL3 teaches a quantum electronic device (Figs. 2(b), 3, 10, 11, 16, 17, 19; sections III, V, VI) comprising: a substrate (SOI wafer) coated with at least one semiconductor block (silicon nanowire) , said semiconductor block extending mainly in a first direction, the semiconductor block comprising a semiconductor layer (Section III, 3 rd para.) ; insulation zones arranged on either side of the semiconductor layer of said semiconductor block (MESA isolation scheme) , a plurality of front gates (G-gates) , each front gate comprising a part extending on regions of the semiconductor layer of said semiconductor block, each of said regions forming a quantum dot, each front gate comprising another part extending on one of the insulation zones (Figs. 2(b), 3; Section III, 3 rd para.) ; one or more exchange electrodes (J-gates) , to modulate the tunnel barrier between neighboring or adjacent quantum dots (Section V, 1 st para.) , said one or more exchange electrodes are arranged between two front gates (Figs. 2(b), 3) , facing and above one of said insulation zones (Fig. 3) , and each exchange electrode is provided with a lower end in contact directly with an insulating material disposed on this insulation zone (dielectric encapsulation; refer to Fig. 3, 10, section III, 3 rd para.) . Re claim 2 , NPL3 teaches wherein at least one first exchange electrode (EXG2) among said exchange electrodes extends above the first insulation zone and at a distance from a first region of said semiconductor block forming a first quantum dot, the first exchange electrode being provided at a distance from a second region of said semiconductor block forming a second quantum dot and so as to allow to modulate a tunnel barrier between said first quantum dot and said second quantum dot (Fig . 19; Section V, 1 st para.) . Re claim 3 , NPL3 teaches wherein said second region of said semiconductor block forms a second quantum dot, the first exchange electrode being juxtaposed with a part of said semiconductor block arranged between said first region and said second region of said semiconductor block (Fig . 19; Section V, 1 st para.) . Re claim 7 , NPL3 teaches wherein the first exchange electrode is provided to control the tunnel barrier between said first quantum dot and said second quantum dot, the device being further provided with at least one additional exchange electrode (EXG1 and/or EXG2) provided to modulate a tunnel barrier between one of said quantum dots and a dopant reservoir formed on and/or in an end portion of the semiconductor block (Fig. 19; Section V, 1 st para.) . Re claim 4 , NPL3 teaches comprising at least one second exchange electrode arranged above a second insulation zone and near said first region forming a first quantum dot and a second region forming a second quantum dot so as to allow to modulate the tunnel barrier between said first quantum dot and said second quantum dot, said second exchange electrode being formed by a second conductive pad having a lower end disposed in contact with an insulating material formed on said second insulation zone (Figs. 3, 10, 16, 19; Section IV-V) . Re claim 5 , NPL3 teaches wherein the first exchange electrode is arranged between a first gate covering said first region and a second gate covering said second region, the first gate and the second gate extending mainly in a second direction orthogonal to the first direction facing the first insulation zone (Figs. 3, 10, 16, 19; Section IV-V) . Re claim 6 , NP3 teaches further comprising at least one other exchange electrode to modulate the tunnel barrier between said second quantum dot and a third quantum dot formed in a third region of said semiconductor block, said other exchange electrode being formed by a third conductive pad, said third conductive pad being formed facing and above the first insulation zone or the second insulation zone (Figs. 3, 10, 16; Section IV-V) . Re claim 8 , NPL3 teaches wherein a second exchange electrode is disposed between the second gate covering said second region and a third gate, the first exchange electrode and the second exchange electrode being independent of one another and not connected to each other (Figs. 3, 10, 16; Sections IV-V) . Re claim 9 , NPL3 teaches wherein said lower end of each exchange electrode is in contact with a dielectric layer in which insulating spacers of the front gates are formed (Fig. 10) . Re claim 10 , NPL3 teaches wherein said semiconductor block is formed in a surface semiconductor layer of a substrate of the semiconductor on insulator type (Section 3, 3 rd para.). Re claim 11 , NPL3 teaches charge reservoirs formed on or in said semiconductor block, the device being advantageously provided with a plurality of charge reservoir electrodes, each contacting a charge reservoir formed on and/or in said semiconductor block (Section 3, 3 rd para.) . Re claim 12 , NPL3 teaches a method for manufacturing a quantum electronic device according to claim 1, the method comprising, in this order, steps of: forming on said substrate said semiconductor block, and insulation zones on either side of said semiconductor block (section III, 3 rd para.) , then forming gate blocks (G-gates) on the semiconductor block, said gate blocks extending mainly in a direction orthogonal to a main direction in which said semiconductor block extends (section III, 3 rd para.) , then forming said one or more exchange electrodes (J-gates) by: depositing an insulating layer (dielectric encapsulation) covering said semiconductor block, said insulation zones and the gate blocks, creating one or more openings passing through said insulating layer, at least one first opening passing through said insulating layer and being made so as to reach an insulating material formed on the first insulation zone (Fig. 3, 10; section III, 3 rd para.) , depositing at least one conductive material in said openings (section III, 3 rd para.) . Re claim 15 , NPL3 teaches wherein among said openings, at least one other opening exposes a doped region (reservoir) of the semiconductor block or formed on said semiconductor block (section III, 3 rd para.) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Bedecarrats et al. (IDS NPL Reference number 3); hereafter referred to as NPL3 in view of Official Notice . Re claim 13 , NPL3 teaches further comprising, before the formation of the insulating layer, steps of: depositing at least one dielectric layer (dielectric spacers, section III, 3 rd para.) , etching said dielectric layer on end portions of the semiconductor block arranged on either side of all of the gate blocks and so as to preserve said dielectric layer on a central portion of said semiconductor block and form insulating spacers against the gate blocks (Fig. 3; while the etching of the dielectric spacer layer is not explicitly disclosed, the Examiner is taking Official Notice that one of ordinary skill in the art at the time of filing would have recognized etching of the layer at one option of arriving at the structure shown in Fig. 3 such that dielectric spacer layer was only present in the central portion of the device ) . Re claim 14 , NPL3 teaches after the etching of said dielectric layer and before the formation of the insulating layer, the formation of doped regions (reservoirs) on said portions of the semiconductor block arranged on either side of all of the gate block (section III, 3 rd para.) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT MOLLY KAY REIDA whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-4237 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 8:30-5:00PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOLLY K REIDA/ Examiner, Art Unit 2899