DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s response filed on 12/31/2025 in which claim 1 is amended and claims 11 to 20 are withdrawn has been entered of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kwak et al. (US Pub. 2009/0034336) in view of Narui (US Pub. 2011/0026348).
Regarding claims 1 and 4, Fig. 5 of Kwak discloses a memory device comprising:
first global bitlines [first 4 Main BL 210 on left side] adjacent to a first edge [Left edge] portion of a memory cell region [200];
second global bitlines [second 4 Main BL 210 on the right] adjacent to a second edge portion [Right edge] of the memory cell region [200];
dummy global bitlines [DBL 220] in a central portion [being sandwiched by first and second global bit lines] of the memory cell region [200]; and
Kwak discloses all claimed invention, but does not specifically shows a bitline sense amplifier in a sense amplifier region and connected to the first global bitlines, the second global bitlines, and the dummy global bitlines, wherein a first layer of the memory cell region is connected to a second layer of the sense amplifier region and is configured to apply a bias voltage to each of the dummy global bitlines. However, having sense amplifiers for a memory device is well known if not inherent. As shows in Fig. 2 and Fig. 3A of Narui, a bitline sense amplifier [SA, Fig. 2] in a sense amplifier region [SAA, Fig. 3A] and connected to the first global bitlines [GBL4], the second global bitlines [GBL5], and the dummy global bitlines [DGBL2], wherein a first layer of the memory cell region [MAT2, Fig. 3A] is connected to a second layer [SAA] of the sense amplifier region [SAA], and by connection of the first layer of the memory cell region [MAT2] to the second layer of the sense amplifier region [SAA], the first layer is configured to apply a bias voltage to each of the dummy global bitlines [since there is voltage input to the dummy global bitline, the memory array or the sense amplifiers inherently applies bias to each global bit lines in order to perform sensing operation].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Narui’s memory device layout with sense amplifier to the teachings of Kwak’s memory having global bit lines and dummy bit lines such that Kwak memory device operates to applies bias voltage to the global bit lines according to Narui’s teachings for the purpose of securing the same memory capacity [paragraph 0011].
Regarding claims 2, Fig. 5 of Kwak discloses wherein a number of each of the first global bitlines [4 lines adjacent to left edge] and the second global bitlines [another 4 lines adjacent to the right edge] is four.
Regarding claim 3, Fig. 5 of Kwak discloses wherein a number of the dummy global bitlines is two [paragraph 0058].
Regarding claims 5-8, Kwak discloses all claimed invention, but does not specifically disclose wherein the first layer is a land pattern layer, wherein the second layer is a bottom poly layer, wherein the first layer is a land pattern layer and the second layer is a bottom poly layer, and wherein a placement of the land pattern layer is based an external shape of the memory cell region, and wherein the land pattern layer includes at least one cut region. However, Fig. 2 of Shin discloses wherein the first layer is a land pattern layer [layer for memory cell array 110 can be called a land pattern layer], wherein the second layer is a bottom poly layer [layer for 142 is a bottom layer], wherein the first layer is a land pattern layer and the second layer is a bottom poly layer, and wherein a placement of the land pattern layer is based an external shape of the memory cell region [the land pattern layer placement is inherently bases on the external shape of the memory region because the land pattern layer is part of the memory region], and wherein the land pattern layer includes at least one cut region [as shows in array 110].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Shin’s memory device layout with sense amplifier to the teachings of Kwak’s memory having global bit lines and dummy bit lines such that Kwak memory device operates to send data on global bit line and dummy bit line according to Shin’s teachings for the purpose of reading data connected to the global bit line and dummy bit lines.
Regarding claim 9, Kwak discloses all claimed all claimed invention, but does not specifically disclose wherein the land pattern layer includes a first land pattern layer adjacent to the sense amplifier region and a second land pattern layer arranged in parallel with the sense amplifier region, and wherein the at least one cut region includes at least one first cut region and at least one second cut region, the first land pattern layer and the second land pattern layer being between the at least one first cut region and the at least one second cut region. However, Fig. 2 of Shin discloses wherein the land pattern layer includes a first land pattern layer [bottom of region 110] adjacent to the sense amplifier region [combination of 130 and 140] and a second land pattern layer [top of array 110] arranged in parallel with the sense amplifier region [combination of 130 and 140], and wherein the at least one cut region includes at least one first cut region [D1] and at least one second cut region [D2], the first land pattern layer and the second land pattern layer being between the at least one first cut region and the at least one second cut region.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Shin’s memory device layout with sense amplifier to the teachings of Kwak’s memory having global bit lines and dummy bit lines such that Kwak memory device operates to send data on global bit line and dummy bit line according to Shin’s teachings for the purpose of reading data connected to the global bit line and dummy bit lines.
Regarding claim 10, Fig. 5 of Kwak discloses wherein each of the dummy global bitlines [DBL] is arranged below the first layer and the second layer in a plan view of the memory device, and wherein each of the dummy global bitlines [DBL] is configured to supply the corresponding bias voltage to the first and second global bitlines [Main BL] without metal contact.
Response to Arguments
Applicant’s arguments with respect to claims 1-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825