DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The objections to the specification have been withdrawn in light of Applicant’s amendments.
Claim Objections
The objections to claims 1 and 11 have been withdrawn in light of Applicant’s amendments.
Response to Arguments
Applicant's arguments filed 9/11/2026 have been fully considered but they are not persuasive. Applicant argues that the newly amended claims are patentable over the applied references because they do not disclose the crystalline silicon-containing liner being doped with an n-type dopant, as recited in the amendment to claim 1. While the Yin reference does not explicitly disclose the silicon liner being doped with an n-type dopant, this is an obvious variation. The silicon liner is doped with a p-type dopant when the device is a p-type device, and thus when making an n-type device, which the Yin reference also contemplates, the liner would be doped with an n-type dopant. Moreover, doping silicon with n-type dopants is used in several other places in the Yin reference, and so this would be a known way to do this. Therefore, while claim 1 is not anticipated by Yin, it is obvious over Yin, and claim 11 is still obvious over Yin in view of Thareja and Lee. See 103 rejections below for more details.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
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Claims 1 and 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yin et al. (US 20220157969 A1), hereinafter referred to as "Yin".
In regards to claim 1, Yin discloses a method of manufacturing an electronic device, the method comprising: forming a crystalline silicon-containing liner within a superlattice structure formed on a top surface of a semiconductor substrate (step 114 in figure 1, which forms 232 in figure 10, paragraph 0024), the superlattice structure comprising a plurality of recessed semiconductor material layers (206 in figure 10) and a corresponding plurality of channel layers (208 in figure 10) alternatingly arranged in a plurality of stacked pairs (figure 10, and paragraph 0014), the crystalline silicon-containing liner formed by a selective epitaxial growth (SEG) process (paragraph 0024. Yin teaches that it is formed by a suitable epitaxial deposition process, and that that process may be selective to semiconductor materials) along the plurality of recessed semiconductor material layers and the corresponding plurality of channel layers (figure 10 and paragraph 0024); and forming an inner spacer directly on the crystalline silicon-containing liner (step 116 in figure 1, which forms 234 in figure 12; paragraph 0026), the inner spacer adjacent a source region and a drain region (212SD in figure 12; paragraph 0019).
Yin does not explicitly disclose that the crystalline silicon-containing liner is doped with an n-type dopant.
Yin discusses both n-type and p-type MBC transistors that can be made (Yin paragraph 0030). Yin further states that when making a p-type device, the semiconductor liner can be doped with a p-type dopant, such as boron (0024). Thus, if making an n-type transistor, the liner would instead be doped with an n-type dopant. Yin also teaches that doping the liner can increase etch resistance of the semiconductor liner or reduce parasitic resistance of the to-be-formed channel members (Yin paragraph 0024). Furthermore, Yin shows that silicon can be doped with n-type dopants, such as phosphorous (P) (Yin paragraph 0033).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the crystalline silicon-containing liner be doped with an n-type dopant when making an n-type transistor in order to increase the etch resistance or reduce the parasitic resistance of the channels.
In regards to claim 5, Yin teaches all of the limitations of claim 1. Yin further discloses that the n-type dopant comprises phosphorous (P) (paragraph 0033).
In regards to claim 6, Yin teaches all of the limitations of claim 1. Yin further discloses that the crystalline silicon-containing liner has a thickness in a range of from 0.5 nm to 3 nm (paragraph 0024).
In regards to claim 7, Yin teaches all of the limitations of claim 1. Yin further discloses that the inner spacer comprises a low-K dielectric material (paragraph 0026).
In regards to claim 8, Yin teaches all of the limitations of claim 1. Yin further discloses that the plurality of recessed semiconductor material layers comprises silicon germanium (SiGe) and the corresponding plurality of channel layers comprise silicon (Si) (paragraph 0014).
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In regards to claim 9, Yin teaches all of the limitations of claim 1. Yin further discloses etching a portion of the inner spacer and a portion of the crystalline silicon-containing liner (step 118 in figure 1, which corresponds to figure 13; paragraph 0027).
In regards to claim 10, Yin teaches all of the limitations of claim 1. Yin further discloses that the electronic device is a gate-all- around (GAA) device (paragraph 0040, the process makes an MBC transistor, which is also referred to as a gate-all-around transistor, see paragraph 0002).
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Yin in view of Thareja et al. (US 20200258997 A1), hereinafter referred to as "Thareja".
In regards to claim 2, Yin teaches all of the limitations of claim 1. Yin does not disclose a preclean step prior to the formation of the liner.
Thareja teaches precleaning the semiconductor substrate prior to forming the crystalline silicon-containing liner (Thareja paragraph 0042, a pre-clean process is performed as a first step before forming any layers in the process chambers). Thareja also teaches that is done to remove contaminants such as carbon or oxide, from the exposed surface of the semiconductor structure, (paragraph 0042).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the precleaning step of Thareja to the method of Yin in order to remove any contaminants from the structure before processing it.
In regards to claim 3, Yin in view of Thareja teaches all of the limitations of claim 2. Yin is silent on the environment/tools used to perform the method.
Thareja teaches precleaning the semiconductor substrate, forming the crystalline silicon-containing liner, and forming the inner spacer are performed in an integrated tool system without vacuum break (Thareja uses a processing system 300, paragraph 0041, in which the pre-clean process as well as several deposition processes are performed without breaking vacuum, paragraph 0042 and 0043). Thareja also teaches that performing all of the processes in the same processing system allows vacuum to not be broken, which decreases the chance of contamination and improves the quality of the deposited epitaxial film.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform the pre-clean, liner forming, and inner spacer forming in an integrated tool as in Thareja in order to decrease the chance of contamination and improve the quality of the deposited films.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yin in view of Yang et al. (US 20230317785 A1), hereinafter referred to as "Yang".
In regards to claim 4, Yin teaches all of the limitations of claim 1. Yin does not explicitly recite what the concentration of the dopant is.
Yang teaches that the concentration of an n-type dopant in a liner layer being greater than 1019 atoms/cm3 keeps the resistance low and can reduce dopant diffusion from subsequently formed overlying main layers into the channel regions, which helps decrease junction leakage (Yang paragraph 0070).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the concentration of the n-type dopant be greater than or equal to 1019 atoms/cm3 in order to keep resistance low and reduce dopant diffusion into the channel regions.
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Claims 11-12 and 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yin in view of Thareja and further in view of Lee et al. (US 20220285533 A1), hereinafter referred to as "Lee".
In regards to claim 11, Yin discloses a method of manufacturing an electronic device, the method comprising: forming a crystalline silicon-containing liner within a superlattice structure formed on a top surface of a semiconductor substrate (step 114 in figure 1, which forms 232 in figure 10, paragraph 0024), the superlattice structure comprising a plurality of recessed semiconductor material layers (206 in figure 10) and a corresponding plurality of channel layers (208 in figure 10) alternatingly arranged in a plurality of stacked pairs (figure 10, and paragraph 14), the crystalline silicon-containing liner formed by a selective epitaxial growth (SEG) process (paragraph 0024. Yin teaches that it is formed by a suitable epitaxial deposition process, and that that process may be selective to semiconductor materials) along the plurality of recessed semiconductor material layers and the corresponding plurality of channel layers (figure 10 and paragraph 0024); forming an inner spacer directly on the crystalline silicon-containing liner (step 116 in figure 1, which forms 234 in figure 12; paragraph 0026), the inner spacer adjacent a source region and a drain region (212SD in figure 12; paragraph 0019); etching a portion of the inner spacer (step 118 in figure 1, which corresponds to figure 13; paragraph 0027); and removing a replacement metal gate and the recessed semiconductor material layers on the semiconductor substrate (Yin figures 18 and 19, dummy gate stack 220 and recessed sacrificial semiconductor layers are removed, see paragraph 0037).
Yin does not explicitly disclose that the crystalline silicon-containing liner is doped with an n-type dopant.
Yin discusses both n-type and p-type MBC transistors that can be made (Yin paragraph 0030). Yin further states that when making a p-type device, the semiconductor liner can be doped with a p-type dopant, such as boron (0024). Thus, if making an n-type transistor, the liner would instead be doped with an n-type dopant. Yin also teaches that doping the liner can increase etch resistance of the semiconductor liner or reduce parasitic resistance of the to-be-formed channel members (Yin paragraph 0024). Furthermore, Yin shows that silicon can be doped with n-type dopants, such as phosphorous (P) (Yin paragraph 0033).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the crystalline silicon-containing liner be doped with an n-type dopant when making an n-type transistor in order to increase the etch resistance or reduce the parasitic resistance of the channels.
Yin does not disclose the first step being precleaning a semiconductor substrate, nor etching an inner sidewall portion of the crystalline silicon-containing liner after removing the semiconductor layers.
Thareja teaches precleaning the semiconductor substrate prior to forming the crystalline silicon-containing liner (Thareja paragraph 0042, a pre-clean process is performed as a first step before forming any layers in the process chambers). Thareja also teaches that is done to remove contaminants such as carbon or oxide, from the exposed surface of the semiconductor structure, (paragraph 0042).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the precleaning step of Thareja to the method of Yin in order to remove any contaminants from the structure before processing it.
Thareja does not teach etching an inner sidewall portion of the silicon liner.
Lee teaches etching an inner sidewall portion of the crystalline silicon-containing liner (Lee figure 10A, sidewalls of silicon cap layer 502 in the interior part of the structure where the sacrificial layers were removed are etched, paragraph 0043) following the removal step of the semiconductor material layers (paragraph 0042). Lee also teaches that the sheet trim process that etches this sidewall portion is done to remove intermixed layers at the interface between the channel and sacrificial epitaxial layers, which enhances device performance (Lee paragraph 0044).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the sheet trim step of Lee which etches the sidewalls in order to remove intermixed layers at the boundary of the channel and sacrificial layer to enhance device performance.
In regards to claim 12, Yin in view of Thareja and further in view of Lee teaches all of the limitations of claim 11. Yin is silent on the environment/tools used to perform the method.
Thareja teaches precleaning the semiconductor substrate, forming the crystalline silicon-containing liner, and forming the inner spacer are performed in an integrated tool system without vacuum break (Thareja uses a processing system 300, paragraph 0041, in which the pre-clean process as well as several deposition processes are performed without breaking vacuum, paragraph 0042 and 0043). Thareja also teaches that performing all of the processes in the same processing system allows vacuum to not be broken, which decreases the chance of contamination and improves the quality of the deposited epitaxial film.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform the pre-clean, liner forming, and inner spacer forming in an integrated tool as in Thareja in order to decrease the chance of contamination and improve the quality of the deposited films.
In regards to claim 14, Yin in view of Thareja and further in view of Lee teaches all of the limitations of claim 11. Yin further discloses that the n-type dopant comprises phosphorous (P) (paragraph 0033).
In regards to claim 15, Yin in view of Thareja and further in view of Lee teaches all of the limitations of claim 11. Yin further discloses that the crystalline silicon-containing liner has a thickness in a range of from 0.5 nm to 3 nm (paragraph 0024).
In regards to claim 16, Yin discloses all of the limitations of claim 11. Yin further discloses that the inner spacer comprises a low-K dielectric material (paragraph 0026).
In regards to claim 17, Yin discloses all of the limitations of claim 11. Yin further discloses that the plurality of recessed semiconductor material layers comprises silicon germanium (SiGe) and the corresponding plurality of channel layers comprises silicon (Si) (paragraph 0014).
In regards to claim 18, Yin discloses all of the limitations of claim 11. Yin further discloses that the electronic device is a gate-all- around (GAA) device (paragraph 0040, the process makes an MBC transistor, which is also referred to as a gate-all-around transistor, see paragraph 0002).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yin in view of Thareja and Lee, and further in view of Yang.
In regards to claim 13, Yin in view of Thareja and further in view of Lee teaches all of the limitations of claim 11. Yin does not explicitly recite what the concentration of the dopant is.
Yang teaches that the concentration of an n-type dopant in a liner layer being greater than 1019 atoms/cm3 keeps the resistance low and can reduce dopant diffusion from subsequently formed overlying main layers into the channel regions, which helps decrease junction leakage (Yang paragraph 0070).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the concentration of the n-type dopant be greater than or equal to 1019 atoms/cm3 in order to keep resistance low and reduce dopant diffusion into the channel regions.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL K ELLIOTT whose telephone number is (571)357-4606. The examiner can normally be reached Mon-Fri 8:00 -5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL KURT ELLIOTT/ Examiner, Art Unit 2899
/Brent A. Fairbanks/ Supervisory Patent Examiner, Art Unit 2899
