DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
• In paragraph 0005, line 1, “One of challenges” should read “One of the challenges”
• In paragraph 0007, line 10 “the inner spacer adjacent a source region” should read “the inner spacer adjacent to a source region”.
• In paragraph 0008, line 10 “the inner spacer adjacent a source region” should read “the inner spacer adjacent to a source region”
• In paragraph 0053, line 5, “any method of method of depositing” should read “any method of depositing”.
• In paragraph 0055, line 9, “250has” should read “250 has”
Appropriate correction is required.
Claim Objections
Claims 1 and 11 objected to because of the following informalities: “the inner spacer adjacent a source region” should read “the inner spacer adjacent to a source region”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
PNG
media_image1.png
614
832
media_image1.png
Greyscale
PNG
media_image2.png
613
446
media_image2.png
Greyscale
PNG
media_image3.png
620
450
media_image3.png
Greyscale
Claim(s) 1 and 4-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yin et al. (US 20220157969 A1), hereinafter referred to as "Yin".
In regards to claim 1, Yin discloses a method of manufacturing an electronic device, the method comprising: forming a crystalline silicon-containing liner within a superlattice structure formed on a top surface of a semiconductor substrate (step 114 in figure 1, which forms 232 in figure 10, paragraph 0024), the superlattice structure comprising a plurality of recessed semiconductor material layers (206 in figure 10) and a corresponding plurality of channel layers (208 in figure 10) alternatingly arranged in a plurality of stacked pairs (figure 10, and paragraph 0014), the crystalline silicon-containing liner formed by a selective epitaxial growth (SEG) process (paragraph 0024. Yin teaches that it is formed by a suitable epitaxial deposition process, and that that process may be selective to semiconductor materials) along the recessed semiconductor material layers and the corresponding plurality of channel layers (figure 10 and paragraph 0024); and forming an inner spacer directly on the crystalline silicon-containing liner (step 116 in figure 1, which forms 234 in figure 12; paragraph 0026), the inner spacer adjacent a source region and a drain region (212SD in figure 12; paragraph 0019).
In regards to claim 4, Yin discloses all of the limitations of claim 1. Yin further discloses that the crystalline silicon-containing liner is doped with a dopant, the dopant comprising a p-type dopant or an n-type dopant (it can be doped with a p-type dopant, paragraph 0024).
In regards to claim 5, Yin discloses all of the limitations of claim 4. Yin further discloses that the p-type dopant comprises boron (B) (paragraph 0024).
In regards to claim 6, Yin discloses all of the limitations of claim 1. Yin further discloses that the crystalline silicon-containing liner has a thickness in a range of from 0.5 nm to 3 nm (paragraph 0024).
In regards to claim 7, Yin discloses all of the limitations of claim 1. Yin further discloses that the inner spacer comprises a low-K dielectric material (paragraph 0026).
In regards to claim 8, Yin discloses all of the limitations of claim 1. Yin further discloses that the semiconductor material layers comprise silicon germanium (SiGe) and the channel layers comprise silicon (Si) (paragraph 0014).
PNG
media_image4.png
625
448
media_image4.png
Greyscale
In regards to claim 9, Yin discloses all of the limitations of claim 1. Yin further discloses etching a portion of the inner spacer and a portion of the crystalline silicon-containing liner (step 118 in figure 1, which corresponds to figure 13; paragraph 0027).
In regards to claim 10, Yin discloses all of the limitations of claim 1. Yin further discloses that the electronic device is a gate-all- around (GAA) device (paragraph 0040, the process makes an MBC transistor, which is also be referred to as a gate-all-around transistor, see paragraph 0002).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yin in view of Thareja et al. (US 20200258997 A1), hereinafter referred to as "Thareja".
In regards to claim 2, Yin discloses all of the limitations of claim 1. Yin does not disclose a preclean step prior to the formation of the liner.
Thareja teaches precleaning the semiconductor substrate prior to forming the crystalline silicon-containing liner (Thareja paragraph 0042, a pre-clean process is performed as a first step before forming any layers in the process chambers). Thareja also teaches that is done to remove contaminants such as carbon or oxide, from the exposed surface of the semiconductor structure, (paragraph 0042).
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the precleaning step of Thareja to the method of Yin in order to remove any contaminants from the structure before processing it.
In regards to claim 3, Yin in view of Thareja teaches all of the limitations of claim 2. Yin is silent on the environment/tools used to perform the method.
Thareja teaches precleaning the semiconductor substrate, forming the crystalline silicon-containing liner, and forming the inner spacer are performed in an integrated tool system without vacuum break (Thareja uses a processing system 300, paragraph 0041, in which the pre-clean process as well as several deposition processes are performed without breaking vacuum, paragraph 0042 and 0043). Thareja also teaches that performing all of the processes in the same processing system allows vacuum to not be broken, which decreases the chance of contamination and improves the quality of the deposited epitaxial film.
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform the pre-clean, liner forming, and inner spacer forming in an integrated tool as in Thareja in order to decrease the chance of contamination and improve the quality of the deposited films.
PNG
media_image5.png
491
438
media_image5.png
Greyscale
PNG
media_image6.png
482
451
media_image6.png
Greyscale
PNG
media_image7.png
676
588
media_image7.png
Greyscale
Claim(s) 11-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yin in view of Thareja and further in view of Lee et al. (US 20220285533 A1), hereinafter referred to as "Lee".
In regards to claim 11, Yin discloses a method of manufacturing an electronic device, the method comprising: forming a crystalline silicon-containing liner within a superlattice structure formed on a top surface of a semiconductor substrate (step 114 in figure 1, which forms 232 in figure 10, paragraph 0024), the superlattice structure comprising a plurality of recessed semiconductor material layers (206 in figure 10) and a corresponding plurality of channel layers (208 in figure 10) alternatingly arranged in a plurality of stacked pairs (figure 10, and paragraph 14), the crystalline silicon-containing liner formed by a selective epitaxial growth (SEG) process (paragraph 0024. Yin teaches that it is formed by a suitable epitaxial deposition process, and that that process may be selective to semiconductor materials) along the recessed semiconductor material layers and the corresponding plurality of channel layers (figure 10 and paragraph 0024); forming an inner spacer directly on the crystalline silicon-containing liner (step 116 in figure 1, which forms 234 in figure 12; paragraph 0026), the inner spacer adjacent a source region and a drain region (212SD in figure 12; paragraph 0019); etching a portion of the inner spacer (step 118 in figure 1, which corresponds to figure 13; paragraph 0027); and removing a replacement metal gate and the recessed semiconductor material layers on the semiconductor substrate (Yin figures 18 and 19, dummy gate stack 220 and recessed sacrificial semiconductor layers are removed, see paragraph 0037).
Yin does not disclose the first step being precleaning a semiconductor substrate, nor etching an inner sidewall portion of the crystalline silicon-containing liner after removing the semiconductor layers.
Thareja teaches precleaning the semiconductor substrate prior to forming the crystalline silicon-containing liner (Thareja paragraph 0042, a pre-clean process is performed as a first step before forming any layers in the process chambers). Thareja also teaches that is done to remove contaminants such as carbon or oxide, from the exposed surface of the semiconductor structure, (paragraph 0042).
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the precleaning step of Thareja to the method of Yin in order to remove any contaminants from the structure before processing it.
Thareja does not teach etching an inner sidewall portion of the silicon liner.
Lee teaches etching an inner sidewall portion of the crystalline silicon-containing liner (Lee figure 10A, sidewalls of silicon cap layer 502 in the interior part of the structure where the sacrificial layers were removed are etched, paragraph 0043) following the removal step of the semiconductor material layers (paragraph 0042). Lee also teaches that the sheet trim process that etches this sidewall portion is done to remove intermixed layers at the interface between the channel and sacrificial epitaxial layers, which enhances device performance (Lee paragraph 0044).
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the sheet trim step of Lee which etches the sidewalls in order to remove intermixed layers at the boundary of the channel and sacrificial layer to enhance device performance.
In regards to claim 12, Yin in view of Thareja and further in view of Lee teaches all of the limitations of claim 11. Yin is silent on the environment/tools used to perform the method.
Thareja teaches precleaning the semiconductor substrate, forming the crystalline silicon-containing liner, and forming the inner spacer are performed in an integrated tool system without vacuum break (Thareja uses a processing system 300, paragraph 0041, in which the pre-clean process as well as several deposition processes are performed without breaking vacuum, paragraph 0042 and 0043). Thareja also teaches that performing all of the processes in the same processing system allows vacuum to not be broken, which decreases the chance of contamination and improves the quality of the deposited epitaxial film.
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform the pre-clean, liner forming, and inner spacer forming in an integrated tool as in Thareja in order to decrease the chance of contamination and improve the quality of the deposited films.
In regards to claim 13, Yin in view of Thareja and further in view of Lee teaches all of the limitations of claim 11. Yin further discloses that the crystalline silicon-containing liner is doped with a p-type dopant or an n-type dopant (it can be doped with a p-type dopant, paragraph 0024).
In regards to claim 14, Yin in view of Thareja and further in view of Lee teaches all of the limitations of claim 13. Yin further discloses that the p-type dopant comprises boron (B) (paragraph 0024).
In regards to claim 15, Yin in view of Thareja and further in view of Lee teaches all of the limitations of claim 11. Yin further discloses that the crystalline silicon-containing liner has a thickness in a range of from 0.5 nm to 3 nm (paragraph 0024).
In regards to claim 16, Yin discloses all of the limitations of claim 11. Yin further discloses that the inner spacer comprises a low-K dielectric material (paragraph 0026).
In regards to claim 17, Yin discloses all of the limitations of claim 11. Yin further discloses that the semiconductor material layers comprise silicon germanium (SiGe) and the channel layers comprise silicon (Si) (paragraph 0014).
In regards to claim 18, Yin discloses all of the limitations of claim 11. Yin further discloses that the electronic device is a gate-all- around (GAA) device (paragraph 0040, the process makes an MBC transistor, which is also be referred to as a gate-all-around transistor, see paragraph 0002).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL K ELLIOTT whose telephone number is (571)357-4606. The examiner can normally be reached Mon-Fri 8:00 -5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL KURT ELLIOTT/ Examiner, Art Unit 2899
/Brent A. Fairbanks/ Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights