Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
However, should applicant desire to perfect the priority claim, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on December 13, 2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner except as otherwise indicated.
Specification
4. The disclosure is objected to because of the following informalities:
In paragraph [0032], line 2, "stack 10" should read "stack 20"
In paragraph [0052], lines 21 and 22, "SiGe' layer 21" should read "SiGe layer 21' ".
Appropriate correction is required.
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 1, 3-4, 6-7, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 2013/0240957 A1, hereafter Lee) in view of Uejima (US 2008/0296614 A1) and Ma et al (US 2005/0186765 A1, hereafter Ma).
Regarding claim 1, Lee discloses in FIGS. 3A-3E a method for manufacturing a field effect transistor (TPMOS) comprising a silicon- germanium active layer (561, [0078]) and a gate oxide layer (58 [0075]) disposed on the active layer (561), the method comprising:
providing a stack including a substrate (Fig. 3A 51, [0064]), a silicon-germanium first layer (FIG. 3C 560 [0075]) disposed on the substrate (51);
forming the gate oxide layer (Fig. 3C 58, [0075]) on the stack (51/560);
subjecting the stack (51/560) to annealing (Fig. 3D 59, [0078]) so as to melt a region (all of 560) of the stack (51/560);
said region (all of 560) comprising at least one part (560B; [0078]) of the first layer (560), and recrystallizing (Fig. 3D 59, [0078]) the molten region (all of 560) of the stack (51/560) to obtain the silicon-germanium active layer (Fig. 3D 59, [0078]) in contact with the gate oxide layer (58), the active layer (Fig. 3E 561) having a germanium concentration gradient ([0076] and [0078]);
wherein the gate oxide layer (58) is formed (Fig. 3C) before annealing (59) or during the annealing.
[AltContent: textbox ( For the record, the inserted figure (modified Fig. 3C of Lee) depicts the plasma oxidation step by the method from Lee modified by Uejima. A stack, consisting of a substrate (51), a first silicon-germanium (SiGe) layer, and a second silicon layer (2) of Uejima, is subjected to plasma oxidation (57), forming the gate oxide layer (58).)]
PNG
media_image1.png
749
975
media_image1.png
Greyscale
Lee fails to disclose a silicon second layer disposed on the first layer (561); laser annealing; and wherein the gate oxide layer (58) is formed before the laser annealing or during the laser annealing.
However, Uejima discloses a stack, the stack comprising a first silicon-germanium layer and a second silicon layer (Fig. 20B 2, [0007]) disposed on the silicon-germanium layer before a heat treatment. Ma discloses laser annealing (Fig 3 140, [0026]) the layers of polysilicon in a stack ([0021]). Uejima and Ma are analogous to Lee in the field of semiconductors and their manufacturing.
PNG
media_image3.png
836
878
media_image3.png
Greyscale
[AltContent: textbox ( For the record, the inserted figure (modified Fig. 3E of Lee) depicts the final semiconductor device fabricated by the method from Lee modified by Uejima. An active channel (561) is formed between a source (S) and a drain (D) with a gate dielectric layer (58) sandwiched between the active channel and a gate electrode (42).)]Thus, it would have been obvious to a one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Lee of first adding the silicon layer on the silicon-germanium, as disclosed by Uejima, such that a second silicon layer disposed on the first layer, creating a strained channel which increases its mobility (Uejima; [0005]-[0007]), and further modifying the method of Lee by using the laser annealing of Ma, instead of the annealing process of Lee to provide localized precise temperature control in melting the stack structure.
Lastly, the structure of Lee and Uejima and Ma is substantially identical to the claimed invention, and made in a substantially identical manner. It would be expected that the resultant structure of the method Lee and Uejima and Ma would exhibit the characteristics of a crystallized silicon-germanium with a germanium concentration gradient, establishing a prima facie case of obviousness (refer to MPEP § 2112.02).
Regarding claim 3, Lee, Uejima, and Ma disclose the method according to claim 1, wherein the silicon layer has a thickness between 0.2 and 15 nm (Uejima [0103]).
Regarding claim 4, Lee, Uejima, and Ma disclose the method according to claim 1, wherein the silicon layer has a thickness between 0.8 and 6 nm (Uejima [0103]).
Regarding claim 6, Lee, Uejima, and Ma disclose the method according to claim 1, wherein a stack (modified Lee Fig 3C 51/560/2) contains a silicon-germanium layer (Lee Fig 3C 560) with a germanium concentration between 0% to 100% concentration (Uejima [0006]).
Thus, it would have been obvious to a one having ordinary skill in the art before the effective filing date of the claimed invention to modify the silicon-germanium layer of Lee, Uejima, and Ma to have a germanium concentration ranging from 0% to 100%, providing the ability to tune carrier mobility.
Regarding claim 7, Lee, Uejima, and Ma disclose the method according to claim 1, wherein a stack (modified Lee Fig 3C 51/560/2) contains a silicon-germanium layer (Lee Fig 3C 560) with a germanium concentration between 0% to 100% concentration (Uejima [0006]).
Thus, it would have been obvious to a one having ordinary skill in the art before the effective filing date of the claimed invention to modify the silicon-germanium layer of Lee, Uejima, and Ma to have a germanium concentration ranging from 0% to 100%, providing the ability to tune carrier mobility.
Regarding claim 13, Lee, Uejima, and Ma disclose the method according to claim 1, wherein a gate electrode (Lee Fig. 3E 60, [0081]) is formed on a gate oxide layer (Lee Fig. 3E 58, [0081]), and a source (Lee Fig. 3E S, [0081]) and a drain (Lee Fig. 3E D, [0081]) are formed.
8. Claims 2, 5, and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Uejima, and Ma as applied to claim 1 above, and further in view of Jiang (CN 113299548 A).
Regarding claim 2, Lee, Uejima, and Ma disclose the method according to claim 1, a gate oxide layer (Lee Fig. 3C 58, [0075]) is formed through plasma oxidation (Lee Fig 3C 57, [0075]).
Lee, Uejima, and Ma fail to disclose oxidation of the silicon layer (modified Lee Fig 3C 2).
However, Jiang discloses a gate oxide layer formed by thermal oxidation of silicon (Jiang Page 3, step S1). Jiang is analogous to Lee in the field of semiconductors and their manufacturing.
Thus, it would have been obvious to a one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the plasma oxidation step of Lee, Uejima, and Ma with the thermal oxidation of silicon, as disclosed by Jiang, to provide better control over the thickness of the gate oxide layer and improve device performance.
Regarding claim 5, Lee, Uejima, and Ma disclose the method according to claim 1, wherein a gate oxide layer (Fig. 3C 58, [0075]) is formed.
Lee, Uejima, and Ma fail to disclose that the gate oxide layer (58) consists of silicon dioxide or the thickness of the gate oxide layer.
However, Jiang discloses a gate oxide layer formed from silicon dioxide (Jiang Page 3, step S1) with a thickness between 0.5 nm to 6 nm (Jiang Page 3, step S1).
Thus, it would have been obvious to a one having ordinary skill in the art before the effective filing date of the claimed invention to form the gate oxide layer of Lee, Uejima, and Ma from silicon dioxide within the thickness range disclosed by Jiang to produce a well-known (MPEP 2144.03) insulator for the gate electrode.
Regarding claim 8, Lee, Uejima, and Ma disclose the method according to claim 1.
Lee, Uejima, and Ma fail to disclose depositing a high dielectric constant (hereafter high-k) dielectric layer onto the gate oxide layer (Lee Fig. 3C 58, [0075]).
However, Jiang discloses depositing a high-k dielectric layer (Page 3, step S1) onto the gate oxide layer (Page 3, step S2).
Thus, it would have been obvious to a one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Lee, Uejima, and Ma to deposit the high-k dielectric layer onto the gate oxide layer, as disclosed by Jiang, to provide improved device performance by reducing leakage current and lowering power consumption.
Regarding claim 9, Lee, Uejima, and Ma disclose the method according to claim 1.
Lee, Uejima, and Ma fail to disclose depositing the high-k dielectric layer onto a gate oxide layer (Fig. 3C 58, [0075]).
However, Jiang discloses depositing a high-k dielectric layer (Page 3, step S1) onto the gate oxide layer (Page 3, step S2) before laser annealing (Page 3, step S3).
Thus, it would have been obvious to a one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Lee, Uejima, and Ma to deposit the high-k dielectric layer onto the gate oxide layer before laser annealing, as disclosed by Jiang, to provide improved device performance and prevent lower dielectric constant dielectric material from forming.
9. Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Uejima, and Ma as applied to claim 1 above, and further in view of Monflier et al ("Investigation of oxygen penetration during UV nanosecond laser annealing of silicon at high energy densities", Applied Surface Science, January 19, 2021; hereafter Monflier).
Regarding claim 10, Lee, Uejima, and Ma disclose the method according to claim 1, wherein the stack (modified Lee Fig 3C 51/560/2) is subjected to laser annealing (Lee Fig. 3D 59, [0078]; Ma Fig 3 140, [0026]).
Lee, Uejima, and Ma fail to disclose exposing the stack (51/560/2) to laser radiation having a wavelength between 200 nm and 600 nm and an energy density between 0.1 J/cm2 and 10 J/cm2 for duration between 10 ns and 1000 ns.
However, Monflier discloses a wavelength between 200 nm and 600 nm (Section 2.1, Paragraph 2) and an energy density between 0.1 J/cm2 and 10 J/cm2 (Section 2.1, Paragraph 2) for duration between 10 ns and 1000 ns (Section 2.1, Paragraph 2). Monflier is analogous to Lee in the field of semiconductors and their manufacturing.
Thus, it would have been obvious to a one having ordinary skill in the art before the effective filing date of the claimed invention to try the laser annealing parameters of Monflier in the methods disclosed by Lee, Uejima, and Ma to produce a substantially identical semiconductor device.
Regarding claim 11, Lee, Uejima, and Ma disclose the method according to claim 1, wherein the stack (modified Lee Fig 3C 51/560/2) is subjected to laser annealing (Lee Fig. 3D 59, [0078]; Ma Fig 3 140, [0026]).
Lee, Uejima, and Ma fail to disclose performing the laser annealing in an oxygen-devoid atmosphere.
Monflier discloses laser annealing in an oxygen-devoid atmosphere (Section 2.1, Paragraph 4).
Thus, it would have been obvious to a one having ordinary skill in the art before the effective filing date of the claimed invention to modify the methods of Lee, Uejima, and Ma to laser anneal in an oxygen-devoid atmosphere to prevent adsorption of unwanted impurities during the annealing process.
10. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, Uejima, and Ma as applied to claim 1 above, and further in view of Halliyal et al (US 6783591 B1, hereafter Halliyal).
Regarding claim 12, Lee, Uejima, and Ma disclose the method according to claim 1, wherein the stack (modified Lee Fig 3C 51/560/2) is subjected to laser annealing (Lee Fig. 3D 59, [0078]; Ma Fig 3 140, [0026]).
Lee, Uejima, and Ma fail to disclose performing laser annealing in an oxygen-containing atmosphere to simultaneously form the gate oxide layer.
However, Halliyal discloses laser annealing performed during the deposition of the gate oxide layer (Column 2, Lines 63-65) in an oxygen-containing environment (Column 4, Lines 23-26).
Thus, it would have been obvious to a one having ordinary skill in the art before the effective filing date of the claimed invention to modify the methods of Lee, Uejima, and Ma to laser anneal in an oxygen-containing atmosphere to simultaneously form the gate oxide layer, as disclosed by Halliyal, to provide gate oxide layers with uniform thickness, improving device performance with minimized process steps.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL B SUN whose telephone number is (571)699-0231. The examiner can normally be reached Mon-Fri 8:00 AM - 5:00 PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL B SUN/Examiner, Art Unit 2892
/ERIC W JONES/Primary Examiner, Art Unit 2892