DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (U.S. Pub. 2017/0062321) [Hereafter “Choi”] in view of Lee et al. (U.S. Pub. 2022/0068853) [Hereafter “Lee”].
Regarding claim 19, Choi [Figs.1-2] discloses a semiconductor package comprising:
a package substrate [10] including a plurality of pads [6] exposed on an upper surface;
a semiconductor device [20] on the package substrate, and including a semiconductor substrate, a plurality of edge pads [135c] adjacent to a first edge of the semiconductor substrate and exposed externally, and a plurality of redistribution patterns [130] connected to the plurality of edge pads; and
a plurality of wires [8] crossing the first edge and connecting the plurality of pads [6] and the plurality of edge pads [135c].
Choi [Para.111] discloses a redistribution pattern [130] may serve as a signal line, power line, or a ground line. However, Choi fails to explicitly disclose the semiconductor device connected to a first edge power pad configured to receive a first power supply voltage and a second edge power pad configured to receive a second power supply voltage lower than the first power supply voltage among the plurality of edge pads, and including edge clamp circuits adjacent to the first edge.
However, Lee [Figs.1-8] discloses a semiconductor package wherein the semiconductor device [20] connected to a first edge power pad [DP1] configured to receive a first power supply voltage and a second edge power pad [DP2] configured to receive a second power supply voltage lower than the first power supply voltage [Para.45; power voltages and signal/ground volatges] among the plurality of edge pads, and including edge clamp circuits [TR] adjacent to the first edge [Figs.3-4] [Para.43 discloses an electrostatic discharge (ESD) protection circuit may be constituted by a transistor TR].
It would have been obvious to combine Choi and Lee to provide the power supply pads and clamp circuit as claimed, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 20, Choi [Para.111] discloses a redistribution pattern [130] may serve as a signal line, power line, or a ground line. Choi [Fig.2] discloses a semiconductor package wherein the semiconductor device [20] includes a plurality of center pads [110], and a first redistribution pattern [130] connected to the first edge power pad [135c] and a second redistribution pattern [130] connected to the second edge power pad [135c] are separated from the plurality of center pads [Fig.2 discloses some center pads 110 not connected to 130].
Allowable Subject Matter
Claims 1-18 are allowed.
The following is an examiner’s statement of reasons for allowance: Prior art does not fairly disclose or make obvious the claimed device/method taken as a whole, and specifically, the limitations of
[Claim 1] a peripheral circuit area including an input/output circuit, a center electrostatic discharge (ESD) clamp circuit, and control logic;
a plurality of center pads above the peripheral circuit area in a vertical direction, orthogonal to an upper surface of the semiconductor substrate, and electrically connected to the input/output circuit and the center ESD clamp circuit;
a plurality of edge pads adjacent to a first edge of the semiconductor substrate and higher than the plurality of center pads in the vertical direction; and
a plurality of redistribution patterns extending in a first direction, parallel to the upper surface of the semiconductor substrate, and connected to the plurality of edge pads in the first direction,
at least one redistribution pattern, among the plurality of redistribution patterns, being connected to at least one uppermost wiring pattern at the same height as the plurality of center pads by a plurality of uppermost vias, on both sides of the plurality of center pads in the first direction.
[Claim 13] a device region having a semiconductor substrate, a plurality of bank regions including a plurality of memory cells on the semiconductor substrate, and a peripheral circuit area including a plurality of semiconductor elements on the semiconductor substrate;
a wiring region including a plurality of wiring patterns connected to the plurality of semiconductor elements and a plurality of center pads connected to the plurality of wiring patterns, and on the device region; and
a redistribution region including a plurality of redistribution patterns connected to at least a portion of the plurality of wiring patterns, and a plurality of edge pads connected to the plurality of redistribution patterns and adjacent to a first edge of the semiconductor substrate, and above the wiring region,
the device region including a first clamp circuit area adjacent to the first edge and below the plurality of edge pads, and a second clamp circuit area below the plurality of center pads.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art is considered analogous art and discloses at least some of the claimed subject matter of the current invention. However, the prior art does not fairly disclose or make obvious the claimed device/method taken as a whole as highlighted above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BAC H AU whose telephone number is (571)272-8795. The examiner can normally be reached M-F 9:00AM-6:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BAC H AU/Primary Examiner, Art Unit 2898
Prosecution Insights