Prosecution Insights
Last updated: April 19, 2026
Application No. 18/538,445

WAFER EVALUATION METHOD, WAFER PRODUCTION METHOD AND DEVICE PRODUCTION METHOD

Non-Final OA §103
Filed
Dec 13, 2023
Examiner
FRANK, RODNEY T
Art Unit
2855
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Resonac Corporation
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
3y 3m
To Grant
76%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allow Rate
663 granted / 913 resolved
+4.6% vs TC avg
Minimal +4% lift
Without
With
+3.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
23 currently pending
Career history
936
Total Applications
across all art units

Statute-Specific Performance

§101
3.8%
-36.2% vs TC avg
§103
43.9%
+3.9% vs TC avg
§102
21.2%
-18.8% vs TC avg
§112
25.6%
-14.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 913 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections Applicant is advised that should claim 8 be found allowable, claim 11 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m). The reverse would also be true. Applicant is advised that should claim 9 be found allowable, claim 12 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m). The reverse would also be true. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3 and 5-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishida et al. (U.S. Patent Application Publication Number 2015/0267296; hereinafter referred to as Nishida) , and further in view of Ma et al. (U.S. Patent Application Publication Number 2004/0206891; hereinafter referred to as Ma . ) With respect to claim 1, Nishida discloses and illustrates a wafer evaluation method, comprising: installing a SiC wafer or a SiC epitaxial wafer (200) on a porous plate having a plurality of through holes (see at least Figures 3 – 8) ; installing a lid on a second surface opposite to a first surface of the SiC wafer or the SiC epitaxial wafer (203) with an O-ring (221) therebetween; supplying a gas into a space surrounded by the second surface (gas supply pipes 232a-d) , the O-ring and the lid and pressurizing the inside of the space (see at least paragraph [0074] of Nishida ) ; and measuring the pressure in the space after a certain period has elapsed (pressure sensor 245). Nishida however fails to disclose inspecting whether there is a threading defect in the SiC wafer or the SiC epitaxial wafer. However, Ma discloses that “R eflective light source 11 is disposed adjacent to scanning plate 16 so that light is reflected from reflective light source 11 onto wafer 14 and received by CCD 12. Distortions of the reflective light are caused by defects in the wafer, especially the epitaxial layer, and recorded by the CCD. Therefore, the defects can be identified through distortions of the reflective light. ” (See Ma paragraph [0021]). Therefore, it would have been obvious to one skilled in the art at the time the invention was filed to utilize the wafer threaded defect identification process of Ma with the system of Nishida in order to have an effective and improved method to identify defects in the wafer surface. With respect to claim 2, while t he wafer evaluation method according to claim 1, wherein the initial pressure in the space immediately after the gas is supplied is 0.2 MPa or more is disclosed in at least paragraph [0239] of Nishida . With respect to claim 3 , t he wafer evaluation method according to claim 1, wherein the initial pressure in the space immediately after the gas is supplied is 0.3 MPa or less is disclosed in at least paragraph [0239] of Nishida . With respect to claim 5 , t he wafer evaluation method according to claim 1, wherein the O-ring has an inner diameter of 80 mm or less is best illustrated in Figures 1 and 3 of Nishida . With respect to claim 6, t he wafer evaluation method according to claim 1, wherein the wafer is the SiC wafer. The wafer evaluation method according to claim 1, wherein the wafer is the SiC epitaxial wafer. With respect to claim 7, a wafer production method, comprising an evaluation process using the wafer evaluation method according to claim 1 is deemed as disclosed as there is nothing in claim 7 that is not in claim 1 above, and thus the same rejection would apply here . With respect to claim 8, while Nishida does not quite disclose t he wafer production method according to claim 8, further comprising an image screening process for checking whether there is the threading defect, wherein the image screening process is performed before the evaluation process. However, Ma discloses an image screening process. Therefore, it would have been obvious to one skilled in the art at the time the invention was filed to utilize the wafer threaded defect imaging process of Ma with the system of Nishida in order to have an effective and improved method to identify defects in the wafer surface. With respect to claim, 9 while Nishida does not quite disclose t he wafer production method according to claim 9, wherein the evaluation process includes a screening process for screening a wafer having the threading defect with an area of larger than 0 µm² and 182 µm² or less when itis determined that there is the threading defect in the image screening process. However, Ma discloses an image screening process. Therefore, it would have been obvious to one skilled in the art at the time the invention was filed to utilize the wafer threaded defect imaging process of Ma with the system of Nishida in order to have an effective and improved method to identify defects in the wafer surface. With respect to claim 1 1 , a device production method, comprising an evaluation process using the wafer evaluation method according to claim 1 is deemed as disclosed as there is nothing in claim 11 claim that is not in claim 1 above, and thus the same rejection would apply here . With respect to claim 12 , while Nishida does not quite disclose t he device production method according to claim 11, further comprising an image screening process for checking whether there is the threading defect, wherein the image screening process is performed before the evaluation process. However, Ma discloses an image screening process. Therefore, it would have been obvious to one skilled in the art at the time the invention was filed to utilize the wafer threaded defect imaging process of Ma with the system of Nishida in order to have an effective and improved method to identify defects in the wafer surface. With respect to claim 13 , while Nishida does not quite disclose t he device production method according to claim 12, further comprising a device producing process, wherein the evaluation process includes a screening process for screening a wafer having the threading defect with an area of larger than 0 µm² and 182 µm² or less in the evaluation process when it is determined that there is the threading defect in the image screening process, and wherein, in the device producing process, a device is produced using a wafer having the threading defect with an area of larger than 0 µm² and 182 µm² or less . However, Ma discloses an image screening process. Therefore, it would have been obvious to one skilled in the art at the time the invention was filed to utilize the wafer threaded defect imaging process of Ma with the system of Nishida in order to have an effective and improved method to identify defects in the wafer surface. Allowable Subject Matter Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to suggest, disclose, or show to be obvious t he wafer evaluation method according to claim 1, wherein, when the difference between the initial pressure in the space immediately after the gas is supplied and the holding pressure in the space after a certain period has elapsed is more than 1/100 of the initial pressure, it is determined that there is the threading defect. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT RODNEY T FRANK whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-2193 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 9am-5:30pm . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Peter Macchiarolo can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-2375 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RODNEY T FRANK/ Examiner, Art Unit 2855 DATE \@ "MMMM d, yyyy" March 19, 2026
Read full office action

Prosecution Timeline

Dec 13, 2023
Application Filed
Mar 21, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12590944
METHOD AND APPARATUS FOR DETERMINING KETOSIS
2y 5m to grant Granted Mar 31, 2026
Patent 12584936
PIPETTING UNIT WITH CAPACITIVE LIQUID DETECTION, COMBINATION OF SUCH A PIPETTING UNIT AND A PIPETTING TIP, AND METHOD FOR CAPACITIVELY DETECTING PIPETTING LIQUID
2y 5m to grant Granted Mar 24, 2026
Patent 12584839
POINT-OF-USE DEVICES AND METHODS FOR DETERMINING RHEOLOGICAL PROPERTIES OF SAMPLES
2y 5m to grant Granted Mar 24, 2026
Patent 12584776
PROCESS MONITORING DEVICE
2y 5m to grant Granted Mar 24, 2026
Patent 12584891
GAS CHROMATOGRAPH
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
76%
With Interview (+3.6%)
3y 3m
Median Time to Grant
Low
PTA Risk
Based on 913 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month