Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-9 in the reply filed on May 19, 2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 13, 2023 is in compliance with time for filing requirements of 3 7 C.F.R. 1.97, and thus, the information disclosure statement has been considered except as otherwise indicated.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description:
Figs. 5, 12C-E, 13A-C, and 13E: element 510 is not defined in the spec.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Pre-Scored Optical Sensor Package with Protective Dam and Transparent Lid.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7-9, 21, 27-28, 29-30, 32 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamamoto et al. (US20210305300A1).
Regarding Claim 1:
Yamamoto discloses an apparatus (chip; Fig. 57), comprising:
a photodetector (Fig. 57 elements 74-79) on a substrate (elements 71 and 73);
a transparent lid (element 81) spaced apart (paragraph 177) from the photodetector by a gap (Figs. 57 and 59 elements 80 and 641);
a notch (groove; Fig. 6 elements 111) formed in an upper surface of the substrate (element 73, paragraph 193);
a plurality of electrical contacts (connection terminal; Fig. 54 elements 613) coupled (paragraphs 510 and 638) to a lower surface of the substrate (element 71);
a through-silicon via (Fig. 37 elements 404) being used to electrically couple (paragraphs 495 and 638) the photodetector (element 401, paragraph 493) to the plurality of electrical contacts (elements 405);
a solder mask (Fig. 57 element 622) in contact (paragraphs 510 and 653) with a lower surface of the substrate (element 71); and
an insulating material (element 80, paragraph 177) disposed between the transparent lid (element 81) and the substrate, the insulating material filling the notch to form a dam (Fig. 4, paragraphs 194-199).
Regarding Claim 2:
Yamamoto discloses an apparatus (chip; Fig. 57) according to claim 1, wherein the notch (Figs. 2 and 6 element 111) is formed at a singulation point (scribe section; elements 91, paragraph 209) in the substrate (element 73).
Regarding Claim 3:
Yamamoto discloses an apparatus (chip; Fig. 57) according to claim 1, wherein a pair of grooves (Figs. 2 and 6 elements 111) is formed at a singulation point (scribe section; elements 91, paragraph 209) in the substrate (element 73).
Regarding Claim 4:
Yamamoto discloses an apparatus (chip; Fig. 57) according to claim 1, wherein the electrical contacts are solder balls (paragraph 510).
Regarding Claim 7:
Yamamoto discloses an apparatus (chip; Fig. 57) according to claim 1, wherein the transparent lid (Fig. 60 element 81) is spaced apart from the photodetector (elements 74-79) by an air cavity (element 641, paragraphs 717-722).
Regarding Claim 8:
Yamamoto discloses an apparatus (chip; Fig. 57) according to claim 7, wherein the insulating material (Fig. 60 elements 635) is configured to prevent moisture from entering the air cavity (paragraphs 723-733).
Regarding Claim 9:
Yamamoto discloses an apparatus (chip; Fig. 57) according to claim 1, wherein the transparent lid (Fig. 57 element 81) is spaced apart from the photodetector (elements 74-79) by an insulating layer (element 80, paragraph 177).
Regarding Claim 21:
Yamamoto discloses an apparatus (chip; Fig. 57), comprising:
an optical sensor die (Fig. 8 elements 71-73, 75, and 78) including a photodetector (elements 74-79) on a top surface of the optical sensor die, the optical sensor die having a stepped profile (see annotated Fig. below) including upper sidewalls and lower sidewalls (Fig. 8 paragraph 200);
a dam (adhesive layer; Fig. 8 element 80) covering the upper sidewalls and at least a portion of the top surface of the optical sensor die (paragraphs 195-196);
a transparent lid (Fig. 8 element 81) disposed on the dam (paragraph 177) , wherein the dam provides a gap between the transparent lid and the photodetector (Figs. 57 and 59 elements 80 and 641); and
an insulating layer (solder resist; Fig. 57 element 622, paragraph 510) disposed on a bottom surface of the optical sensor die (elements 71 and 622).
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Regarding Claim 27:
Yamamoto discloses an apparatus (chip; Fig. 57) according to claim 21, wherein the gap includes an air cavity (Fig. 60 element 641) above the photodetector (elements 74-79).
Regarding Claim 28:
Yamamoto discloses an apparatus (chip; Fig. 57) according to claim 21, wherein an entirety of the gap is filled by the dam (Fig. 5 element 80, paragraphs 194-197).
Regarding Claim 29:
Yamamoto discloses an apparatus (chip; Fig. 57), comprising:
a photodetector (Fig. 57 elements 74-79) on a substrate (elements 71 and 73);
a recess (groove; Fig. 8 elements 131) formed in an upper surface of the substrate (element 73, paragraph 193);
a dam (adhesive layer; element 80, paragraph 177) in the recess and on at least a portion of the upper surface of the substrate (Fig. 8, paragraphs 194-201);
a transparent lid (Fig. 8 element 81) supported by the dam (paragraph 177) and spaced apart from the photodetector by a gap (Figs. 8 and 60 elements 80 and 641); and
a solder mask (Fig. 57 element 622) in contact (paragraphs 510 and 653) with a lower surface of the substrate (element 71).
Regarding Claim 30:
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Yamamoto discloses an apparatus (chip; Fig. 57) according to claim 29, wherein the recess includes a groove spaced apart from a sidewall (Fig. 37; see annotated Fig. below) of the substrate (element 401, paragraph 493), a first portion of the dam (element 80) being disposed in the groove and a second portion of the dam being disposed on the upper surface of the substrate (paragraphs 194-201).
Regarding Claim 32:
Yamamoto discloses an apparatus (chip; Fig. 57) according to claim 29, wherein the gap includes an air cavity (Fig. 60 element 641, paragraphs 717-722), and wherein the dam is configured to prevent moisture from entering the air cavity (paragraphs 723-733).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6, 22-26, 31 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (US20210305300A1) in view of Hsu et al. (US20210098324A1).
Regarding Claim 5:
Yamamoto discloses an apparatus (chip; Fig. 57) according to claim 1, but does not explicitly teach where the solder mask includes a redistribution layer.
Hsu, however, discloses an analogous chip scale package (Fig. 1 element 100), wherein the solder mask (element 8, paragraph 25) includes a redistribution layer (element 7, paragraph 25).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the apparatus described in Yamamoto further in view of Hsu to explicitly include a solder mask that further includes a redistribution layer because both are directed to analogous optical devices. Doing so reinforces structural support and protection for the device during manufacturing (Hsu, paragraph 2).
Regarding Claim 6:
Yamamoto discloses an apparatus (chip; Fig. 57) according to claim 1, but does not explicitly teach where the solder mask wraps around the sides of the substrate.
Hsu, however, discloses an analogous chip scale package (Fig. 1 element 100), wherein the solder mask (element 8) wraps around three sides of the substrate (element 1).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the apparatus described in Yamamoto further in view of Hsu to explicitly include a solder mask that wraps around three sides of the substrate because both are directed to analogous optical devices. Doing so reinforces structural support and protection for the device during manufacturing (Hsu, paragraphs 2 and 27).
Regarding Claim 22:
Yamamoto discloses an apparatus (chip; Fig. 57) according to claim 21, but does not explicitly teach where the insulating layer includes a redistribution layer.
Hsu, however, discloses an analogous chip scale package (Fig. 1 element 100), wherein the insulating layer (element 8, paragraph 25) includes a redistribution layer (element 7, paragraph 25).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the apparatus described in Yamamoto further in view of Hsu to explicitly include an insulating layer that further includes a redistribution layer because both are directed to analogous optical devices. Doing so reinforces structural support and protection for the device during manufacturing (Hsu, paragraph 2).
Regarding Claim 23:
The combination of Yamamoto and Hsu discloses an apparatus according to claim 22, further comprising: a plurality of electrical contacts (connection terminal; Fig. 57 element 623) coupled to the bottom surface of the optical sensor die through the insulating layer (element 622, paragraphs 638 and 696).
Regarding Claim 24:
The combination of Yamamoto and Hsu discloses an apparatus according to claim 23, wherein the optical sensor die includes a through-silicon via (Fig. 37 elements 404) being used to electrically couple (paragraphs 495 and 638) the photodetector (element 401, paragraph 493) to the plurality of electrical contacts (elements 404);
Regarding Claim 25:
Yamamoto discloses an apparatus (chip; Fig. 57) according to claim 21, but does not explicitly teach where the insulating layer wraps around the lower sidewalls.
Hsu, however, discloses an analogous chip scale package (Fig. 1 element 100), wherein the insulating layer (element 8) wraps around the sidewalls (element 1).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the apparatus described in Yamamoto further in view of Hsu to explicitly include an insulating layer that wraps around the lower sidewalls of the optical sensor die because both are directed to analogous optical devices. Doing so reinforces structural support and protection for the device during manufacturing (Hsu, paragraphs 2 and 27).
Regarding Claim 26:
The combination of Yamamoto and Hsu discloses an apparatus according to claim 25, wherein a lower portion of the dam (Fig. 106 elements 80 and 1314) is disposed on a portion of the insulating layer (element 1312, paragraph 1328-1330).
Regarding Claim 31:
Yamamoto discloses an apparatus (chip; Fig. 57) according to claim 30, but does not explicitly teach where a wrapping portion is disposed on a sidewall of the substrate nor where a portion of the dam is disposed on the wrapping porting.
Hsu, however, discloses an analogous chip scale package (Fig. 1 element 100), wherein a wrapping portion of the solder mask (element 8, paragraph 25) is disposed on a sidewall of the substrate (element 1), wherein a third portion of the dam is disposed on the wrapping portion (element 3, paragraphs 22-25).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the apparatus described in Yamamoto further in view of Hsu to explicitly include a wrapping portion of the solder mask that is disposed on a sidewall of a substrate wherein a third portion of the dam is disposed on the wrapping portion because both are directed to analogous optical devices. Doing so reinforces structural support and protection for the device during manufacturing (Hsu, paragraphs 2 and 27).
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chang et al. (US 20210210539 A1), Wu et al. (US 20200152681 A1), Wu et al. (US 9960197 B1), Nagata et al. (US 20180019277 A1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Chloë E Benton whose telephone number is (571)272-9976. The examiner can normally be reached Monday-Thursday: 8am-6pm EST.
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/Chloë E Benton/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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