Prosecution Insights
Last updated: April 19, 2026
Application No. 18/538,580

BROADBAND ABSORPTIVE TERMINATION IN DIODE SWITCHES

Non-Final OA §103
Filed
Dec 13, 2023
Examiner
PERENY, TYLER J
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
OA Round
3 (Non-Final)
95%
Grant Probability
Favorable
3-4
OA Rounds
2y 2m
To Grant
99%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allow Rate
154 granted / 162 resolved
+27.1% vs TC avg
Moderate +6% lift
Without
With
+5.8%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
25 currently pending
Career history
187
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
57.3%
+17.3% vs TC avg
§102
20.6%
-19.4% vs TC avg
§112
20.5%
-19.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 162 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed 03/16/2026 have been fully considered but they are not persuasive. Applicant’s arguments with respect to the bias nodes of claims 1, 7, & 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Regarding claims 1 & 14, in response to applicants’ arguments that Mahmood (US 2014/0120968 A1) in view of Shapiro et al. (US 2017/0230049 A1), hereinafter Shapiro, does not teach the termination leg and its incorporation would render the tank circuit (see figure 1, element 40) of Mahmood inoperable, this is not persuasive because if the prior art structure is capable of performing the intended use, then it meets the claimed limitation. Applicant provides no evidence to the contrary that the prior art presented does not perform the intended use, and one of ordinary skill in the art would recognize that incorporating a termination leg within the RF switch would perform the function of absorbing the applied RF signal without undue experimentation. Thus, the termination leg electrically coupled between the second node and ground (termination switch 608 in combination with resistor R, Para [0051]) is disclosed by Shapiro, in figure 6A, as required by the invention as claimed. Additionally, in response to applicants’ argument that Shapiro does not teach the series diode, and that its inclusion would render the antenna switch inoperable, this is not persuasive. Shapiro discloses, in figure 6A, the series diode (Para [0073], switch 606 [illustrated as a FET switch]…”embodiments of the invention described above have used FET switches…other switch technologies may be used, including PIN diodes”). In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the manner in which the series diode is connected and how the diode would be biased for operation) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). In response to applicants’ argument that the series diode of Shapiro would render the antenna switch of Mahmood inoperable, if the prior art structure is capable of performing the intended use, then it meets the claimed limitation. Applicant provides no evidence to the contrary that the prior art presented does not perform the intended use, and one of ordinary skill in the art would recognize that incorporating the series PIN diode would perform the function of controlling the flow of RF energy without undue experimentation. Thus, the series diode electrically coupled between the first node and the second node (switch 606 that may be a PIN diode between the first node formed at shunt switch 604 and second node formed at termination leg comprised of resistor R and switch 608) is disclosed by Shapiro, in figure 6A, as required by the invention as claimed. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-5, 7-10, 12-18, & 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mahmood (US 2014/0120968 A1) in view of Shapiro et al. (US 2017/0230049 A1), hereinafter Shapiro, and further in view of Puente et al. (US 2021/0135326 A1), hereinafter Puente. Regarding claim 1, Mahmood discloses, in figure 1, A diode switch, comprising: a common port (14), a first port (16), and a second port (20); a first switch arm electrically coupled between the first port and the common port (first arm from port 16 to port 14); and a second switch arm electrically coupled between the second port and the common port (second arm from port 20 to port 14), wherein the first switch arm comprises: a first node (second node formed at the intersection to elements 24 and 34) and a second node (44) each electrically coupled between and electrically separated from the first port and the common port (first and second node are coupled between and electrically separated from port 16 and port 14); a shunt diode electrically coupled between the first node and ground (shunt diode 24 coupled between the first node and ground, but fails to disclose a first bias node electrically coupled to the first node; a second bias node electrically coupled to the second node; a termination leg electrically coupled between the second node and ground; and a series diode electrically coupled between the first node and the second node. However, Shapiro discloses, in figure 6A, the first switch arm (600) comprising a termination leg (Para [0051], “termination switch 608”) electrically coupled between the second node and ground (termination leg comprised of resistor R and switch 608); and a series (606) diode (Para [0073], “while the embodiments of the invention described above have used FET switches…other switch technologies may be used, including PIN diodes”) electrically coupled between the first node and the second node (606 coupled between first node formed at shunt switch 604 and second node formed at termination leg comprised of resistor R and switch 608). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the components of Shapiro in the switch of Mahmood, to achieve the benefit of implementing an RF switch with greater isolation by terminating a signal through a switch arm when the arm path is non-conductive (Shapiro, Para [0050] & [0051]). In combination, Mahmood and Shapiro fail to disclose a first bias node electrically coupled to the first node; and a second bias node electrically coupled to the second node; However, Puente discloses, in figure 2, a first bias node electrically coupled to the first node (bias node 204 electrically coupled to the first node defined as the intersection to inductor L3); and a second bias node electrically coupled to the second node (bias node 208 electrically coupled to the second node defined as the intersection to diode D4); It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the bias nodes of Puente in the switch arm of Mahmood and Shapiro, to achieve the benefit of biasing the diodes of the switch arm of the switching system to function in a desired transmit or receive mode (Puente, Para [0003]). Regarding claim 2, the combination of Mahmood, Shapiro, and Puente disclose the diode switch according to claim 1, and Shapiro continues to disclose, in figures 6A & 6B, wherein the diode switch comprises an absorptive switch (Para [0052], “absorptive switch architecture”). Regarding claim 3, the combination of Mahmood, Shapiro, and Puente disclose the diode switch according to claim 1, and Shapiro continues to disclose, in figure 6A & 6B, a second series diode (Para [0073], “while the embodiments of the invention described above have used FET switches…other switch technologies may be used, including PIN diodes”) electrically coupled between the common port and the first node (series switch 602 coupled between first node formed at shunt switch 604 and the common port RFC), wherein the diode switch comprises an absorptive switch without a quarter-wavelength transmission line (Para [0052], “absorptive switch architecture”…a quarter-wavelength transmission line is not present). Regarding claim 4, the combination of Mahmood, Shapiro, and Puente disclose the diode switch according to claim 1, and Mahmood continues to disclose, in figure 1, a transmission line electrically coupled between the common port and the first node (1/4 wave transmission line 18 coupled between port 14 and the node formed at the intersection of elements 24 & 34). Regarding claim 5, the combination of Mahmood, Shapiro, and Puente disclose the diode switch according to claim 1, and Shapiro continues to disclose, in figure 6A, wherein the termination leg comprises a second shunt diode (Para [0073], “while the embodiments of the invention described above have used FET switches…other switch technologies may be used, including PIN diodes”) and a resistor electrically coupled in series between the second node and ground (shunt switch 608 and resistor R coupled in series between the second node and ground). Regarding claim 7, The combination of Mahmood, Shapiro, and Puente disclose the diode switch of claim 1, and Mahmood continues to disclose, in figure 1, wherein the second switch arm comprises: a third node (node formed at the intersection to elements 26 and 34) and a fourth node (54) each electrically coupled between and electrically separated from the second port and the common port (third and fourth node are coupled between and electrically separated from port 20 and port 14); a second shunt diode electrically coupled between the third node and ground (shunt diode 26 coupled between the third node and ground), but fails to disclose a third bias node electrically coupled to the third node; a fourth bias node electrically coupled to the fourth node; a second termination leg electrically coupled between the fourth node and ground; and a second series diode electrically coupled between the third node and the fourth node. However, Shapiro discloses, in figure 1 & 6A, the second switch arm (Para [0050], “the high throw-count RF switch embodiments described above have simple series-shunt switching elements 103. However, in some applications requiring greater isolation, additional circuitry may be needed. For example, FIG. 6A is a block diagram of a high-isolation series-shunt switching element 600 connected to a common port RFC through an inductor L as one branch of a high throw-count RF switch”…600 duplicated on branch extending to the right of RFC) comprising a second termination leg (Para [0051], “termination switch 608”) electrically coupled between the fourth node and ground (termination leg comprised of resistor R and switch 608); and a second series (606) diode (Para [0073], “while the embodiments of the invention described above have used FET switches…other switch technologies may be used, including PIN diodes”) electrically coupled between the third node and the fourth node (606 coupled between first node formed at shunt switch 604 and second node formed at termination leg comprised of resistor R and switch 608). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the components of Shapiro in the second switch arm of Mahmood, to achieve the benefit of implementing an RF switch with greater isolation by terminating a signal through the second switch arm when the second arm path is non-conductive (Shapiro, Para [0050] & [0051]). In combination, Mahmood and Shapiro fail to disclose a third bias node electrically coupled to the third node; and a fourth bias node electrically coupled to the fourth node. However, Puente discloses, in figure 2, a third bias node electrically coupled to the third node (third bias node 202 electrically coupled to the third node defined at the intersection to inductor L2); and a fourth bias node electrically coupled to the fourth node (fourth bias node 206 electrically coupled to the fourth node defined at the intersection to diode D3). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the bias nodes of Puente in the second switch arm of Mahmood and Shapiro, to achieve the benefit of biasing the diodes of the switch arm of the switching system to function in a desired transmit or receive mode (Puente, Para [0003]). Regarding claim 8, the combination of Mahmood, Shapiro, and Puente disclose the diode switch according to claim 7, and Shapiro continues to disclose, in figure 6A & 6B, a third series diode (Para [0073], “while the embodiments of the invention described above have used FET switches…other switch technologies may be used, including PIN diodes”) electrically coupled between the common port and the third node (series switch 602 coupled between first node formed at shunt switch 604 and the common port RFC, as present in second series arm switch to the right of port RFC), Regarding claim 9, the combination of Mahmood, Shapiro, and Puente disclose the diode switch according to claim 7, and Mahmood continues to disclose, in figure 1, a transmission line electrically coupled between the common port and the third node (1/4 wave transmission line 22 coupled between port 14 and the node formed at the intersection of elements 34 & 26). Regarding claim 10, the combination of Mahmood, Shapiro, and Puente disclose the diode switch according to claim 7, and Shapiro continues to disclose, in figure 6A, wherein the second termination leg comprises a third shunt diode (Para [0073], “while the embodiments of the invention described above have used FET switches…other switch technologies may be used, including PIN diodes”) and a resistor electrically coupled in series between the fourth node and ground (shunt switch 608 and resistor R coupled in series between the second node and ground, as present in second series arm switch to the right of port RFC). Regarding claim 12, the combination of Mahmood, Shapiro, and Puente disclose the diode switch according to claim 1, and Shapiro continues to disclose, in figure 1 & 6A, a third port (RF3); and a third switch arm electrically coupled between the third port and the common port (third switch arm 600 would be coupled between the third port RF3 and the common port RFC). Regarding claim 13, the combination of Mahmood, Shapiro, and Puente disclose the diode switch of claim 1, and Mahmood continues to disclose, in figure 1, wherein the second switch arm comprises: a third node (node formed at the intersection to elements 26 and 34) and a fourth node (54) each electrically coupled between and electrically separated from the second port and the common port (third and fourth node are coupled between and electrically separated from port 20 and port 14); a second shunt diode electrically coupled between the third node and ground (shunt diode 26 coupled between the third node and ground); and a transmission line electrically coupled between the third node and the fourth node (1/4 wave transmission line 22 coupled between port 14 and the node formed at the intersection of elements 34 & 26), but fails to disclose a second termination leg electrically coupled between the fourth node and ground; and a second series diode electrically coupled between the third node and the fourth node. However, Shapiro discloses, in figure 1 & 6A, the second switch arm (Para [0050], “the high throw-count RF switch embodiments described above have simple series-shunt switching elements 103. However, in some applications requiring greater isolation, additional circuitry may be needed. For example, FIG. 6A is a block diagram of a high-isolation series-shunt switching element 600 connected to a common port RFC through an inductor L as one branch of a high throw-count RF switch”…600 duplicated on branch extending to the right of RFC) comprising a second termination leg (Para [0051], “termination switch 608”) electrically coupled between the fourth node and ground (termination leg comprised of resistor R and switch 608); and a second series (606) diode (Para [0073], “while the embodiments of the invention described above have used FET switches…other switch technologies may be used, including PIN diodes”) electrically coupled between the third node and the fourth node (606 coupled between first node formed at shunt switch 604 and second node formed at termination leg comprised of resistor R and switch 608). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the components of Shapiro in the second switch arm of Mahmood and Puente, to achieve the benefit of implementing an RF switch with greater isolation by terminating a signal through the second switch arm when the second arm path is non-conductive (Shapiro, Para [0050] & [0051]). Regarding claim 14, Mahmood discloses, in figure 1, A diode switch, comprising: a common port (14) and a first port (16); a switch arm electrically coupled between the first port and the common port (first arm from port 16 to port 14), wherein the switch arm comprises: a first node (second node formed at the intersection to elements 24 and 34) and a second node (44) each electrically coupled between and electrically separated from the first port and the common port (first and second node are coupled between and electrically separated from port 16 and port 14); a shunt diode electrically coupled between the first node and ground (shunt diode 24 coupled between the first node and ground, but fails to disclose a first bias node electrically coupled to the first node; a second bias node electrically coupled to the second node; a termination leg electrically coupled between the second node and ground; and a series diode electrically coupled between the first node and the second node. However, Shapiro discloses, in figure 6A, the first switch arm (600) comprising a termination leg (Para [0051], “termination switch 608”) electrically coupled between the second node and ground (termination leg comprised of resistor R and switch 608); and a series (606) diode (Para [0073], “while the embodiments of the invention described above have used FET switches…other switch technologies may be used, including PIN diodes”) electrically coupled between the first node and the second node (606 coupled between first node formed at shunt switch 604 and second node formed at termination leg comprised of resistor R and switch 608). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the components of Shapiro in the switch of Mahmood, to achieve the benefit of implementing an RF switch with greater isolation by terminating a signal through a switch arm when the arm path is non-conductive (Shapiro, Para [0050] & [0051]). In combination, Mahmood and Shapiro fail to disclose a first bias node electrically coupled to the first node; and a second bias node electrically coupled to the second node; However, Puente discloses, in figure 2, a first bias node electrically coupled to the first node (bias node 204 electrically coupled to the first node defined as the intersection to inductor L3); and a second bias node electrically coupled to the second node (bias node 208 electrically coupled to the second node defined as the intersection to diode D4); It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the bias nodes of Puente in the switch arm of Mahmood and Shapiro, to achieve the benefit of biasing the diodes of the switch arm of the switching system to function in a desired transmit or receive mode (Puente, Para [0003]). Regarding claim 15, the combination of Mahmood, Shapiro, and Puente disclose the diode switch according to claim 14, and Shapiro continues to disclose, in figures 6A & 6B, wherein the diode switch comprises an absorptive switch (Para [0052], “absorptive switch architecture”). Regarding claim 16, the combination of Mahmood, Shapiro, and Puente disclose the diode switch according to claim 14, and Shapiro continues to disclose, in figure 6A & 6B, a second series diode (Para [0073], “while the embodiments of the invention described above have used FET switches…other switch technologies may be used, including PIN diodes”) electrically coupled between the common port and the first node (series switch 602 coupled between first node formed at shunt switch 604 and the common port RFC), wherein the diode switch comprises an absorptive switch without a quarter-wavelength transmission line (Para [0052], “absorptive switch architecture”…a quarter-wavelength transmission line is not present). Regarding claim 17, the combination of Mahmood, Shapiro, and Puente disclose the diode switch according to claim 14, and Mahmood continues to disclose, in figure 1, a transmission line electrically coupled between the common port and the first node (1/4 wave transmission line 18 coupled between port 14 and the node formed at the intersection of elements 24 & 34). Regarding claim 18, the combination of Mahmood, Shapiro, and Puente disclose the diode switch according to claim 14, and Shapiro continues to disclose, in figure 6A, wherein the termination leg comprises a second shunt diode (Para [0073], “while the embodiments of the invention described above have used FET switches…other switch technologies may be used, including PIN diodes”) and a resistor electrically coupled in series between the second node and ground (shunt switch 608 and resistor R coupled in series between the second node and ground). Regarding claim 20, the combination of Mahmood, Shapiro, and Puente disclose the diode switch of claim 14, and Mahmood continues to disclose, in figure 1, a second port (20); and a second switch arm electrically coupled between the second port and the common port (second arm from port 20 to port 14), wherein the second switch arm comprises: a third node (node formed at the intersection to elements 26 and 34) and a fourth node (54) each electrically coupled between and electrically separated from the second port and the common port (third and fourth node are coupled between and electrically separated from port 20 and port 14); a second shunt diode electrically coupled between the third node and ground (shunt diode 26 coupled between the third node and ground), but fails to disclose a second termination leg electrically coupled between the fourth node and ground; and a second series diode electrically coupled between the third node and the fourth node. However, Shapiro discloses, in figure 1 & 6A, the second switch arm (Para [0050], “the high throw-count RF switch embodiments described above have simple series-shunt switching elements 103. However, in some applications requiring greater isolation, additional circuitry may be needed. For example, FIG. 6A is a block diagram of a high-isolation series-shunt switching element 600 connected to a common port RFC through an inductor L as one branch of a high throw-count RF switch”…600 duplicated on branch extending to the right of RFC) comprising a second termination leg (Para [0051], “termination switch 608”) electrically coupled between the fourth node and ground (termination leg comprised of resistor R and switch 608); and a second series (606) diode (Para [0073], “while the embodiments of the invention described above have used FET switches…other switch technologies may be used, including PIN diodes”) electrically coupled between the third node and the fourth node (606 coupled between first node formed at shunt switch 604 and second node formed at termination leg comprised of resistor R and switch 608). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the components of Shapiro in the second switch arm of Mahmood and Puente, to achieve the benefit of implementing an RF switch with greater isolation by terminating a signal through the second switch arm when the second arm path is non-conductive (Shapiro, Para [0050] & [0051]). Allowable Subject Matter Claims 6 & 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER J PERENY whose telephone number is (571)272-4189. The examiner can normally be reached M-F 7:30-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TYLER J PERENY/Examiner, Art Unit 2843
Read full office action

Prosecution Timeline

Dec 13, 2023
Application Filed
Jun 25, 2025
Non-Final Rejection — §103
Sep 29, 2025
Response Filed
Oct 08, 2025
Final Rejection — §103
Mar 16, 2026
Request for Continued Examination
Mar 19, 2026
Response after Non-Final Action
Mar 26, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Expected OA Rounds
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Grant Probability
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2y 2m
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