DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II in the reply filed on 05/18/2026 is acknowledged.
Status of the Application
Claims 1-20 remain pending in this application. Claims 1-5 and 19-20 are withdrawn.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claim 6 is objected to because of the following informalities:
Claim 6 recites “a top die that on the bottom die”, it appears it should read “a top die appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 7, 9, 10, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al (US 20220262741 A1, here after Tsai) in view of Kim et al (US 20210242101 A1, hereafter Kim).
Regarding claim 6, Tsai, in at least on embodiment, teaches: A semiconductor package (Tsai 4, fig 7, ¶0065-0068) comprising:
a substrate (Tsai 10, ¶0065) including a first surface (Tsai 10a, ¶0065, top of 10) and a second surface (Tsai 10b, ¶0065, bottom of 10) opposite the first surface (Tsai fig 7, ¶0065);
a bottom die (Tsai 20, ¶0065) electrically connected to first bonding pads (Tsai 110, fig 7, ¶0065) on the first surface of the substrate by solder bumps (Tsai 212, ¶0065)(Tsai fig 7);
a top die (Tsai M1, ¶0066) that on the bottom die (as best understood to mean “a top die on the bottom die”)(Tsai fig 7, ¶0066) and electrically connected to second bonding pads (Tsai BF1)(Tsai fig 7, ¶) on the first surface of the substrate by wires (Tsai W1, ¶0066)(Tsai fig 7, ¶0066);
an underfill (Tsai WF, ¶0067) in a gap between the substrate and the bottom die (Tsai fig 7, ¶0067);
a mold (Tsai MC, ¶0068) that at least partially covers elements on the first surface of the substrate (Tsai fig 7, ¶0068); and
a plurality of solder balls (Tsai 60, ¶0068) on the second surface of the substrate (Tsai fig 7, ¶0068),
wherein the second bonding pads and a part of each of the wires bonded to the second bonding pads are immersed in the underfill (Tsai fig 7).
Tsai does not teach: an underfill dam surrounding the first bonding pads and the second bonding pads on the first surface of the substrate and is configured to restrict diffusion of the underfill.
Kim, in the same field of endeavor of semiconductor device manufacturing, teaches: an underfill dam (Kim D, ¶0021) surrounding first bonding pads (Kim 104) on a first surface (Kim top of 102) of a substrate (Kim 102, ¶0021) and is configured to restrict diffusion of an underfill (Kim 120, ¶0022)(Kim fig 1, 2A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Tsai to include the underfill dam of Kim, including surrounding second bonding pads of Tsai, and such that “an underfill dam surrounding the first bonding pads and the second bonding pads on the first surface of the substrate and is configured to restrict diffusion of the underfill”, in order to restrict diffusion of underfill to a specified area (Kim ¶0022-0026) while maintaining corrosion prevention to wires (Tsai ¶0068).
Regarding claim 7, Tsai in view of Kim teaches: The semiconductor package of claim 6, wherein:
the underfill dam (Tsai as modified to include Kim D) has a thickness of 10 μm or more (Kim ¶0046, 18 μm) and has a maximum height lower than a maximum height of the bottom die (Tsai 20, similar to Kim 110)(Kim fig 2A, ¶0046, height of Kim D is bounded to be lower than or equal to the lower surface of 110, therefore its maximum height must be lower than at least a height of the bottom die when both heights are measured from a top surface of the substrate).
Regarding claim 9, Tsai in view of Kim teaches: The semiconductor package of claim 6, wherein:
the second bonding pads (Tsai BF1, similar to Kim 108) extend along at least one side of the bottom die (Tsai 20, similar to Kim 110)(Tsai fig 6, Kim fig 1) and do not extend along at least one other side of the bottom die (Tsai fig 6, Kim fig 1).
Regarding claim 10, Tsai in view of Kim teaches: The semiconductor package of claim 9, wherein:
the second bonding pads (Tsai BF1, similar to Kim 108) are adjacent three sides of the bottom die (Tsai 20, similar to Kim 110)(Kim fig 1), and
a region for implantation of an underfill solution (Kim 114) is provided on the remaining one side of the bottom die (Kim fig 1, ¶0048)(Kim fig 1).
Regarding claim 17, Tsai in view of Kim, in at least one embodiment, teaches: The semiconductor package of claim 6, further comprising an additional chip (Tsai M2, ¶0066) on the top die (Tsai M1)(Tsai fig 7, ¶0066),
wherein a portion of the second bonding pads (Tsai BF1) are electrically connected to the top die (Tsai fig 7), and another portion of the second bonding pads (Tsai BF2) are electrically connected to the additional chip (Tsai fig 7).
Regarding claim 18, Tsai in view of Kim, in at least one embodiment, teaches: The semiconductor package of claim 6, wherein:
the top die comprises a plurality of top dies (Tsai M1, M2, ¶0066, similar to Kim 330a, 330b)(Tsai fig 7, Kim fig 5), and
each of the top dies is electrically connected to adjacent ones of the second bonding pads (Tsai BF1, BF2) by wires (Tsai W1, W2, ¶0067)(Tsai fig 7).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al (US 20220262741 A1, here after Tsai) in view of Kim et al (US 20210242101 A1, hereafter Kim), as applied to claim 7 above, and further in view of Sugiyama et al (JP 2010147225 A, English translation of description provided, hereafter Sugiyama).
Regarding claim 8, Tsai in view of Kim teaches: The semiconductor package of claim 7, wherein the underfill dam (Tsai as modified to include Kim D) is on the first surface of the substrate (Tsai 10a, similar to Kim 102).
Tsai in view of Kim does not teach: the underfill dam is a solder resist (SR).
Sugiyama, in the same field of endeavor of semiconductor device manufacturing, teaches: an underfill dam (Sugiyama 2f, ¶0036) is a solder resist (SR)(Sugiyama ¶0036, 0061) coated on a first surface (Sugiyama 2a) of a substrate (Sugiyama 2)(Sugiyama fig 2, ¶0036).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the underfill dam of Tsai in view of Kim such that it is a solder resist (SR), as taught by Sugiyama, in order to form the underfill dam from a material that is capable of withstanding solder-reflow processing without deformation.
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to a solder resist (SR), which are known and commonly used as underfill dams within semiconductor devices, and that use of conventional materials to perform their known function is prima-facie obvious (See MPEP 2144.07).
Allowable Subject Matter
Claims 11-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 11, it is allowable, notwithstanding above objection, primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
further comprising third bonding pads for wire bonding on the underfill dam. (Applicant fig 7, ¶0091).
Tsai in view of Kim, in at least one embodiment, teaches: The semiconductor package of claim 6, further comprising third bonding pads for wire bonding (Tsai BF2, ¶0066-0067, fig 7).
Neither Tsai, Kim, nor Sugiyama, either alone or in combination, teaches: third bonding pads for wire bonding on the underfill dam, as required by claim 11.
Therefore, Tsai in view of Kim in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Tsai, Kim, Sugiyama, or any other prior arts of record so that all of limitations of claim 11 as a whole can be met.
Regarding claims 12 and 13, the dependent claims are allowed for their dependency to claim 11.
Regarding claim 14, it is allowable, notwithstanding above objection, primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
further comprising third bonding pads for wire bonding outside the underfill dam on the first surface of the substrate. (Applicant fig 9, ¶0098).
Tsai in view of Kim, in at least one embodiment, teaches: The semiconductor package of claim 6, further comprising third bonding pads for wire bonding (Tsai BF2, ¶0066-0067, fig 7).
Neither Tsai, Kim, nor Sugiyama, either alone or in combination, teaches: third bonding pads for wire bonding outside the underfill dam on the first surface of the substrate, as required by claim 14.
Therefore, Tsai in view of Kim in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Tsai, Kim, Sugiyama, or any other prior arts of record so that all of limitations of claim 14 as a whole can be met.
Regarding claims 15 and 16, the dependent claims are allowed for their dependency to claim 14.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Tsao et al (US 20100164091 A1 ), Karhade et al (US 20200051956 A1), Sankman et al (US 20200273783 A1), and Warren et al (US 20200006169 A1) are cited as an examples of analogous devices.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS B. MICHAUD whose telephone number is (703)756-1796. The examiner can normally be reached Monday-Friday, 0800-1700 Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 272-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/EVA Y MONTALVO/Supervisory Patent Examiner, Art Unit 2818
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