DETAILED ACTION
This action is responsive to the following communications: the Amendment filed on June 24, 2026.
Claims 1 and 3-21 are pending. Claim 2 is canceled. Claim 21 is newly added. Claims 1, 10-11 and 17 are amended. Claims 1, 10 and 17 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 6, 8, 10, 12-15, 17 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Melik-Martirosian (US 20120239858).
Regarding independent claim 1, Melik-Martirosian discloses a memory device [Fig. 1: 103, para. 31], comprising:
one or more components [the flash memory includes one or more internal registers 106 and an internal flash controller 107 for communication by external devices, para. 32] configured to:
perform first one or more write operations using a first programming time of a plurality of programming times [see Fig. 4, at beginning of life (BOL), a write operation will take a maximum programming duration 401, para. 40] over which a voltage of a charge is incrementally increased or decreased for one or more cells of the memory device [a NAND memory block is programmed one page at a time using an Incremental Step Pulse Program (ISSP). ISSP increases the threshold voltage VT of selected cells and applies a series of ISPP voltage pulses in a step pattern in which pulse amplitude is incrementally increased with increasing pulse number, para. 35],
wherein the first programming time is associated with a first amount of time for writing data [see Fig. 4, at beginning of life (BOL), a write operation will take a maximum programming duration 401 and the programming time 402 will progressively decrease towards a minimum programming duration 403, producing a programming duration range 404 over a range of P/E cycles, para. 40];
detect a trigger event associated with changing a programming time used by the memory device [trigger event 409 may be a number or range of P/E cycles (for example, every 1,000 cycles after an initial trigger at 500 cycles) or a set duration (for example, programming time 402, erase time 406, or the age of the SSD). Controller 101 monitors these conditions and invokes the trigger when a predetermined condition is reached, para. 40. Controller 101 may be configured to invoke trigger event 409 when programming duration 402 reaches minimum programming duration 403, para. 44];
switch, based on detecting the trigger event, the programming time from the first programming time to a second programming time of the plurality of programming times [on the trigger event, controller 101 may determine and adjust the ISPP and/or ISPE parameters to new values to adjust the programming conditions, para. 42. Controller 101 may determine and adjust the ISPP parameters (for example, to higher levels) to modify programming duration 402 such that its maximum limit is maintained or lowered to a revised maximum duration 410, para. 45],
wherein the second programming time is associated with a second amount of time for writing data [see Fig. 4, controller 101 may determine and adjust the ISPP parameters (for example, to higher levels) to modify programming duration 402 such that its maximum limit is maintained or lowered to a revised maximum duration 410, para. 45], and
wherein switching, based on detecting the trigger event, the programming time from the first programming time to the second programming time includes changing, based on detecting the trigger event, the first amount of time for writing data to the second amount of time for writing data [controller 101 adjusts ISPP parameters to modify programming duration 402 so that its previous maximum/minimum duration is changed to a revised duration, para. 45. See Fig. 8B, a minimum and maximum allowed TPROG were chosen as 1.5 ms and 1.6 ms. Once TPROG falls below a minimum of 1.5 ms, starting program pulse voltage is reduced until TPROG is within allowed limits]; and
perform second one or more write operations using the second programming time [after trigger event 409 and adjustment of the ISPP parameters, controller 101 sets the parameters so that the next programming operation uses the adjusted conditions, para. 48].
Regarding claim 3, Melik-Martirosian discloses wherein the first one or more write operations are associated with a first operation phase of the memory device [see Fig. 4, at beginning of life (BOL), a write operation will take a maximum programming duration 401, para. 40] and the second one or more write operations are associated with a second operation phase of the memory device [after trigger event 409 and adjustment of the ISPP parameters, controller 101 sets the parameters so that the next programming operation uses the adjusted conditions, para. 48].
Regarding claim 6, Melik-Martirosian discloses wherein the one or more components, to detect the trigger event, are configured to:
receive, from a host device, a command indicating that the programming time is to be switched from the first programming time to the second programming time [controller 101 may be configured to communicate with and provide the commands to flash memory 103 via registers 106 (for example, the test register) and/or flash controller 107 to modify the ISPP and/or ISPE parameters of flash memory 103, para. 36. On the trigger event, controller 101 may determine and adjust the ISPP and/or ISPE parameters to new values to adjust the programming conditions, para. 42].
Regarding claim 8, Melik-Martirosian discloses wherein the one or more components, to detect the trigger event, are configured to:
detect that a block erase count, associated with a memory block to be written, satisfies a threshold [trigger event 409 may be a number or range of P/E cycles (for example, every 1,000 cycles after an initial trigger at 500 cycles), para. 41. The trigger event is based on a number or range of P/E cycles, para. 43].
Regarding independent claim 10, Melik-Martirosian discloses a method, comprising:
receiving, by a memory device, a write command indicating data to be programmed [controller 101 is configured to store data received from a host device 104 in flash memory 103 in response to a write command from host device 104, para. 27];
determining, by the memory device, a programming time, from a first programming time, and a second programming time, to be used to program the data [see Fig. 4, controller 101 determines new ISPP parameters and can perform a calculation of programming duration 402 in conjunction with a calculation of the parameters such that programming duration 402 remains within a programming range 404 or reset to maximum programming duration 401 or revised maximum duration 410, para. 53],
wherein the programming time indicates an amount of time for programming the data [at beginning of life (BOL), a write operation will take a maximum programming duration 401. As flash memory 103 is cycled and trapped charge builds up in the memory cells, the programming time 402 will progressively decrease towards a minimum programming duration 403, producing a programming duration range 404 over a range of P/E cycles, para. 40] and over which a voltage of a charge is incrementally increased or decreased for one or more cells of the memory device [a NAND memory block is programmed one page at a time using an Incremental Step Pulse Program (ISSP). ISSP increases the threshold voltage VT of selected cells and applies a series of ISPP voltage pulses in a step pattern in which pulse amplitude is incrementally increased with increasing pulse number, para. 35],
wherein the first programming time is associated with a first amount of time for programming the data [see Fig. 4, at beginning of life (BOL), a write operation will take a maximum programming duration 401 and the programming time 402 will progressively decrease towards a minimum programming duration 403, producing a programming duration range 404 over a range of P/E cycles, para. 40] and the second programming time is associated with a second amount of time for programming the data [see Fig. 4, controller 101 may determine and adjust the ISPP parameters (for example, to higher levels) to modify programming duration 402 such that its maximum limit is maintained or lowered to a revised maximum duration 410, para. 45]; and
programming, by the memory device, the data to a memory of the memory device using the programming time [after the parameters are determined, controller 101 programs flash memory 103 to execute ISPP on the block, providing the adjusted parameters to the flash memory. The programming time condition is monitored during that programming operation, para. 55].
Regarding claim 12, Melik-Martirosian discloses wherein the first programming time is a default programming time [see Fig. 4, at beginning of life (BOL), a write operation will take a maximum programming duration 401, para. 40], and the method further comprises:
receiving, from a host device, a command indicating that the programming time is to be switched from the first programming time to the second programming time [programming parameters can be dynamically determined and/or adjusted at run-time in response to commands received from host 104 via host interface 105, para. 36. On the trigger event, controller 101 may determine and adjust the ISPP and ISPE parameters to new values to adjust the programming conditions, para. 42].
Regarding claim 13, Melik-Martirosian discloses wherein determining the programming time comprises:
determining that the programming time is the second programming time based on receiving the command [programming parameters can be dynamically determined and/or adjusted at run-time in response to commands received from host 104 via host interface 105, para. 36].
Regarding claim 14, Melik-Martirosian discloses wherein determining the programming time comprises:
determining a block erase count;
determining whether the block erase count satisfies a threshold [trigger event 409 may be a number or range of P/E cycles (for example, every 1,000 cycles after an initial trigger at 500 cycles), para. 41. The trigger event is based on a number or range of P/E cycles, para. 43]; and
determining the programming time based on whether the block erase count satisfies the threshold [when the trigger event is met, controller 101 adjusts ISPP parameters to new values, para. 42].
Regarding claim 15, Melik-Martirosian discloses wherein determining the programming time comprises:
determining that the programming time is:
the first programming time if the block erase count does not satisfy the threshold [normal drive operation in which controller 101 monitors P/E cycle count and waits for the trigger event, para. 52], or the second programming time if the block erase count satisfies the threshold [when the trigger event is met, controller 101 adjusts ISPP parameters to new values, para. 42].
Regarding independent claim 17, Melik-Martirosian discloses An apparatus, comprising:
means for performing a first one or more write operations using a first amount of time for a programming time [see Fig. 4, at beginning of life (BOL), a write operation will take a maximum programming duration 401, para. 40], the first amount of time being of a plurality of amounts of time over which a voltage of a charge is incrementally increased or decreased for one or more cells of a memory device [a NAND memory block is programmed one page at a time using an Incremental Step Pulse Program (ISSP). ISSP increases the threshold voltage VT of selected cells and applies a series of ISPP voltage pulses in a step pattern in which pulse amplitude is incrementally increased with increasing pulse number, para. 35],
wherein the programming time indicates an amount of time for performing a write operation from the first one or more write operations [see Fig. 4, at beginning of life (BOL), a write operation will take a maximum programming duration 401 and the programming time 402 will progressively decrease towards a minimum programming duration 403, producing a programming duration range 404 over a range of P/E cycles, para. 40];
means for detecting a trigger event associated with changing the amount of time for the programming time [trigger event 409 may be a number or range of P/E cycles (for example, every 1,000 cycles after an initial trigger at 500 cycles) or a set duration (for example, programming time 402, erase time 406, or the age of the SSD). Controller 101 monitors these conditions and invokes the trigger when a predetermined condition is reached, para. 40. Controller 101 may be configured to invoke trigger event 409 when programming duration 402 reaches minimum programming duration 403, para. 44];
means for performing a second one or more write operations using a second amount of time for the programming time based on detecting the trigger event, the second amount of time being of the plurality of amounts of time [on the trigger event, controller 101 may determine and adjust the ISPP and/or ISPE parameters to new values to adjust the programming conditions, para. 42. Controller 101 may determine and adjust the ISPP parameters (for example, to higher levels) to modify programming duration 402 such that its maximum limit is maintained or lowered to a revised maximum duration 410, para. 45]; and
means for switching, based on detecting the trigger event, the programming time from the first amount of time for the programming time to the second amount of time for the programming time [controller 101 adjusts ISPP parameters to modify programming duration 402 so that its previous maximum/minimum duration is changed to a revised duration, para. 45. See Fig. 8B, a minimum and maximum allowed TPROG were chosen as 1.5 ms and 1.6 ms. Once TPROG falls below a minimum of 1.5 ms, starting program pulse voltage is reduced until TPROG is within allowed limits].
Regarding claim 19, Melik-Martirosian discloses wherein the means for detecting the trigger event comprises:
means for receiving, from a host device, a command indicating that the programming time is to be switched from the first amount of time to the second amount of time [programming parameters can be dynamically determined and/or adjusted at run-time in response to commands received from host 104 via host interface 105, para. 36. On the trigger event, controller 101 may determine and adjust the ISPP and ISPE parameters to new values to adjust the programming conditions, para. 42].
Regarding claim 20, Melik-Martirosian discloses wherein the means for detecting the trigger event comprises:
means for detecting that a block erase count satisfies a threshold [trigger event 409 may be a number or range of P/E cycles (for example, every 1,000 cycles after an initial trigger at 500 cycles), para. 41. The trigger event is based on a number or range of P/E cycles, para. 43].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5, 7, 9, 11, 16, 18 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Melik-Martirosian (US 20120239858) in view of Grin et al. (US 20150178188).
Regarding claim 4, Melik-Martirosian teaches the limitations with respect to claim 1.
However, Melik-Martirosian is silent with respect to wherein the first one or more write operations are associated with writing original equipment manufacturer data or original design manufacturer data, and wherein the second one or more write operations are associated with writing user data.
Grin et al. teach wherein the first one or more write operations are associated with writing original equipment manufacturer data or original design manufacturer data [before the soldering occurs, a production station can preload the storage module 100 with data, such as an operating system or a GPS map, para. 19. A vendor may want to preload another image to the storage module 100, para. 23], and wherein the second one or more write operations are associated with writing user data [the non-volatile memory 120 can be used to store user or other data, para. 18].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Grin et al. to the teachings of Melik-Martirosian such that modifying the memory device of Melik-Martirosian so that the first write operations using a first programming time are used for manufacturer data and the second write operations using a second programming time are used for user data as suggested by Grin et al. to provide reliability programming for data exposed to the manufacturer environment while permitting a different programming condition for user data writes.
Regarding claim 5, Melik-Martirosian in combination with Grin et al. teach the limitations with respect to claim 4.
Furthermore, Melik-Martirosian discloses wherein the first amount of time is greater than the second amount of time [Melik-Martirosian teaches at beginning of life (BOL), a write operation will take a maximum programming duration 401, para. 40. Melik-Martirosian also teaches modifying programming duration to a lower revised maximum duration 410, para. 45].
Regarding claim 7, Melik-Martirosian teaches the limitations with respect to claim 6.
However, Melik-Martirosian is silent with respect to wherein the command is a vendor specific command.
Grin et al. teach the command is a vendor specific command [the command can be a vendor-specific command to perform an operation not specified in the standard, para. 25].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Grin et al. to the teachings of Melik-Martirosian such that employing Grin et al.’s vendor specific command as the host command for invoking Melik-Martirosian’s programming time adjustment, because doing so would permit the host to expressly command a change from one programming time configuration to another while maintaining compatibility with the standard host interface.
Regarding claim 9, Melik-Martirosian teaches the limitations with respect to claim 8.
However, Melik-Martirosian is silent with respect to wherein a value of the threshold is based on a data write size of data associated with the first one or more write operations.
Grin et al. teach a value of the threshold is based on a data write size of data associated with the first one or more write operations [the production station enables the preloading of data and informs the storage module 100 of the size of preloaded data. Controller tracks the amount received and when the count reaches that expected size, the controller knows all expected data has arrived, para. 22].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Grin et al. to the teachings of Melik-Martirosian such that selecting Melik-Martirosian’s threshold based on Grin et al.’s known expected preload data size so that the programming condition change occurs in coordination with the expected amount of manufacturer data being written.
Regarding claim 11, Melik-Martirosian teaches the limitations with respect to claim 10.
However, Melik-Martirosian is silent with respect to wherein determining the programming time is based on a data type associated with the data, wherein the data type includes at least manufacturer data.
Grin et al. teach wherein the first one or more write operations are based on a data type associated with the data, wherein the data type includes at least manufacturer data [before the soldering occurs, a production station can preload the storage module 100 with data, such as an operating system or a GPS map, para. 19. A vendor may want to preload another image to the storage module 100, para. 23].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Grin et al. to the teachings of Melik-Martirosian such that determining Melik-Martirosian’s programming time based on the type of data being programmed, including whether the data is manufacturer data as taught by Grin et al., because doing so would permit the known programming time settings of Melik-Martirosian to be selected according to the known reliability and performance requirements associated with different data types, yielding the predictable result of selecting an appropriate programming time for manufacturer data writes.
Regarding claim 16, Melik-Martirosian teaches the limitations with respect to claim 10.
Furthermore, Melik-Martirosian discloses wherein determining the programming time comprises:
determining an operation phase associated with the memory device ["BOL", "low cycles", "mid cycles", "EOL", para. 43], and
determining the programming time based on the operation phase associated with the memory device [Melik-Martirosian teaches determining and adjusting different programming durations and conditions, para. 45].
However, Melik-Martirosian is silent with respect to the operation phase includes a manufacturing phase or an end user phase.
Grin et al. teach to the operation phase includes a manufacturing phase [before the soldering occurs, a production station can preload the storage module 100 with data, such as an operating system or a GPS map, para. 19. A vendor may want to preload another image to the storage module 100, para. 23] or an end user phase [the non-volatile memory 120 can be used to store user or other data, para. 18].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Grin et al. to the teachings of Melik-Martirosian such that modifying the memory device of Melik-Martirosian so that the first write operations using a first programming time are used for manufacturer data and the second write operations using a second programming time are used for user data as suggested by Grin et al. to provide reliability programming for data exposed to the manufacturer environment while permitting a different programming condition for user data writes.
Regarding claim 18, Melik-Martirosian teaches the limitations with respect to claim 17.
Furthermore, Melik-Martirosian teaches wherein the first amount of time is greater than the second amount of time [Melik-Martirosian teaches at beginning of life (BOL), a write operation will take a maximum programming duration 401, para. 40. Melik-Martirosian also teaches modifying programming duration to a lower revised maximum duration 410, para. 45].
However, Melik-Martirosian is silent with respect to wherein the first one or more write operations are associated with initialization data, wherein the second one or more write operations are associated with user data.
Grin et al. teach wherein the first one or more write operations are associated with initialization data [before the soldering occurs, a production station can preload the storage module 100 with data, such as an operating system or a GPS map, para. 19. A vendor may want to preload another image to the storage module 100, para. 23], and wherein the second one or more write operations are associated with user data [the non-volatile memory 120 can be used to store user or other data, para. 18].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Grin et al. to the teachings of Melik-Martirosian such that modifying the memory device of Melik-Martirosian so that the first write operations using a first programming time are used for initialization data and the second write operations using a second programming time are used for user data as suggested by Grin et al. to provide reliability programming for data during initialization while improving programming performance during normal user operation.
Regarding claim 21, Melik-Martirosian teaches the limitations with respect to claim 10.
However, Melik-Martirosian is silent with respect to wherein determining the programming time is based on a data type associated with the data, wherein the data type includes at least user data.
Grin et al. teach wherein the first one or more write operations are based on a data type associated with the data, wherein the data type includes at least user data [the non-volatile memory 120 can be used to store user or other data, para. 18].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Grin et al. to the teachings of Melik-Martirosian such that determining Melik-Martirosian’s programming time based on the type of data being programmed, including whether the data is user data as taught by Grin et al., because doing so would permit the known programming time settings of Melik-Martirosian to be selected according to the known reliability and performance requirements associated with different data types, yielding the predictable result of selecting an appropriate programming time for user data writes.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 3-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at (571)272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUY H LUONG/Examiner, Art Unit 2825
/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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