DETAILED ACTION
This action is responsive to the following communications: the Amendment filed on February 13, 2026 and the Foreign Priority papers retrieved on December 29, 2022.
Claims 1-20 are pending. Claims 1, 10 and 17 are amended. Claims 1, 10 and 17 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-8, 10, 12-15, 17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Pangal et al. (US 20140082460) in view of McNeil Jr. et al. (US 20220050601).
Regarding independent claim 1, Pangal et al. disclose a memory device [Fig. 1: 100], comprising:
one or more components [Fig. 1: 114, 120, memory/storage 114 includes flash memory such as NAND memory that is coupled to other components of system 100 through a memory controller 120, para. 19] configured to:
perform first one or more write operations [Fig. 4: 402, a first trim profile (e.g., profile A) is applied (e.g., by the controller logic 125), para. 30] over which a voltage of a charge is incrementally increased or decreased for one or more cells of the memory device [the trim profiles may include TEV, R1, PV1, R2, PV2, R3, PV3, program start voltage (Vpgm), erase start voltage (Vera), and the unselected WL (Word Line) read voltage (Vread/Vpassr). The trims above may be decreased with cycles, except Vera which may be increased. Other trims above may be changed independently, para. 26 and 28].
detect a trigger event [Fig. 4: 404, if the current cycle count has reached a first cycle threshold (Cyc 1) or a failure trigger occurs (such as Block Fail Rate (BFR) threshold value or (e.g., near miss) ECC event), para. 30];
switch, based on detecting the trigger event, perform second one or more write operations [Fig. 4: 406, a second trim profile (e.g., profile B) is applied (e.g., by the controller logic 125)].
However, Pangal et al. are silent with respect to perform first one or more write operations using a first programming time of a plurality of programming times, wherein the first programming time is associated with a first amount of time for writing data and perform second one or more write operations using the second programming time, wherein the second programming time is associated with a second amount of time for writing data.
McNeil Jr. et al. teach a tPROG circuitry 112 can be configured to operate the quantity of logical units with one of a plurality of trims that correspond to the selected programming time. Each trim that corresponds to a particular programming time corresponds to a different performance target. The plurality of trims can be stored in a library of trims that are stored with correspondence to programming times, such as in a table or database. The tPROG circuitry 112 can select a trim from the library based on the selected programming time [para. 35]. The tPROG circuitry 112 can select a slowest one of the plurality of programming times that is sufficient to provide the required throughput. Some of the plurality of programming times are slower than a fastest programming time of the non-volatile memory device 116 [para. 32]. Moreover, McNeil Jr. et al. also disclose examples of trims include programming voltages, programming frequency, a program start voltage, a program step voltage, a program inhibit start voltage, and an erase verify voltage [para. 38].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of McNeil Jr. et al. to the teaching of Pangal et al. such that incorporating programming time (tPROG) circuitry of McNeil Jr. et al. that selects a trim from the library based on the selected programming time into Pangal et al.’s memory controller, thereby enabling the controller to perform earlier write operations (trim profile A) with one programming time and later write operations (trim profile B) with another programming time after a trigger event, with expected result of optimizing reliability and performance across life of memory device.
Regarding claim 2, Pangal et al. in combination with McNeil Jr. et al. teach the limitations with respect to claim 1.
Furthermore, McNeil Jr. et al. disclose wherein the programming time used by the memory device indicates an amount of time associated with the memory device performing a write operation [see Fig. 2: 222, the plot 222 is a graph of a programming time requirement (“tPROG REQUIREMENT”) versus an amount of memory requirement (“NAND REQUIREMENT”) that show the programming time necessary to write that amount of memory also increases, para. 42].
Regarding claim 3, Pangal et al. in combination with McNeil Jr. et al. teach the limitations with respect to claim 1.
Furthermore, Pangal et al. disclose wherein the first one or more write operations are associated with a first operation phase of the memory device and the second one or more write operations are associated with a second operation phase of the memory device [see Fig. 4, trim profile A is corresponding to the first operation phase and trim profile B corresponding to the second operation phase, para. 30].
Regarding claim 6, Pangal et al. in combination with McNeil Jr. et al. teach the limitations with respect to claim 1.
Furthermore, McNeil Jr. et al. disclose wherein the one or more components, to detect the trigger event, are configured to:
receive, from a host device, a command indicating that the programming time is to be switched from the first programming time to the second programming time [see Fig. 2, plot 224 illustrates different methods of programming a memory device to store time based telemetric sensor data received from a host. Transitioning from method-A to method-B to method-C, slower programming times are used, which results in greater memory cell endurance, para. 43. A definition of the required throughput can be received from the host upon an initial connection to the host and the memory device can be operated with the selected programming time thereafter, para. 45].
Regarding claim 7, Pangal et al. in combination with McNeil Jr. et al. teach the limitations with respect to claim 6.
Furthermore, McNeil Jr. et al. disclose wherein the command is a vendor specific command [the tPROG circuitry 112 can receive an input (other than from the host system 102) defining the required throughput. Such an input, for example, can be received from a user or received as a parameter from a vendor of the memory sub-system 104, para. 34].
Regarding claim 8, Pangal et al. in combination with McNeil Jr. et al. teach the limitations with respect to claim 1.
Furthermore, Pangal et al. disclose wherein the one or more components, to detect the trigger event, are configured to:
detect that a block erase count, associated with a memory block to be written, satisfies a threshold [the current cycle count has reached a first cycle threshold (Cyc 1) or a failure trigger occurs (such as Block Fail Rate (BFR) threshold value or (e.g., near miss) ECC event), para. 30].
Regarding independent claim 10, Pangal et al. disclose a method, comprising:
receiving, by a memory device, a write command indicating data to be programmed [system 100 may include logic (e.g., NAND controller logic 125) to issue read or write requests to the memory/storage 114, para. 19];
a voltage of a charge is incrementally increased or decreased for one or more cells of the memory device [the trim profiles may include TEV, R1, PV1, R2, PV2, R3, PV3, program start voltage (Vpgm), erase start voltage (Vera), and the unselected WL (Word Line) read voltage (Vread/Vpassr). The trims above may be decreased with cycles, except Vera which may be increased. Other trims above may be changed independently, para. 26 and 28], and
programming, by the memory device, the data to a memory of the memory device [The cache 108 may store data (e.g., including instructions) that are utilized by one or more components of the processor 102-1, such as the cores 106, para. 18].
However, Pangal et al. are silent with respect to determining, by the memory device, a programming time, from a first programming time and a second programming time, to be used to program the data, wherein the programming time indicates an amount of time for programming the data, wherein the first programming time is associated with a first amount of time and the second programming time is associated with a second amount of time.
McNeil Jr. et al. teach a tPROG circuitry 112 can be configured to operate the quantity of logical units with one of a plurality of trims that correspond to the selected programming time. Each trim that corresponds to a particular programming time corresponds to a different performance target. The plurality of trims can be stored in a library of trims that are stored with correspondence to programming times, such as in a table or database. The tPROG circuitry 112 can select a trim from the library based on the selected programming time [para. 35]. The tPROG circuitry 112 can select a slowest one of the plurality of programming times that is sufficient to provide the required throughput. Some of the plurality of programming times are slower than a fastest programming time of the non-volatile memory device 116 [para. 32]. Moreover, McNeil Jr. et al. also disclose examples of trims include programming voltages, programming frequency, a program start voltage, a program step voltage, a program inhibit start voltage, and an erase verify voltage [para. 38].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of McNeil Jr. et al. to the teaching of Pangal et al. such that incorporating programming time (tPROG) circuitry of McNeil Jr. et al. that selects a trim from the library based on the selected programming time into Pangal et al.’s memory controller, thereby enabling the controller to perform earlier write operations (trim profile A) with one programming time and later write operations (trim profile B) with another programming time after a trigger event, with expected result of optimizing reliability and performance across life of memory device.
Regarding claim 12, Pangal et al. in combination with McNeil Jr. et al. teach the limitations with respect to claim 10.
Furthermore, McNeil Jr. et al. disclose wherein the first programming time is a default programming time, and the method further comprises:
receiving, from a host device, a command indicating that the programming time is to be switched from the first programming time to the second programming time [see Fig. 2, plot 224 illustrates different methods of programming a memory device to store time based telemetric sensor data received from a host. Transitioning from method-A to method-B to method-C, slower programming times are used, which results in greater memory cell endurance, para. 43. A definition of the required throughput can be received from the host upon an initial connection to the host and the memory device can be operated with the selected programming time thereafter, para. 45].
Regarding claim 13, Pangal et al. in combination with McNeil Jr. et al. teach the limitations with respect to claim 12.
Furthermore, McNeil Jr. et al. disclose wherein determining the programming time comprises:
determining that the programming time is the second programming time based on receiving the command [a definition of the required throughput can be received from the host upon an initial connection to the host and the memory device can be operated with the selected programming time thereafter, para. 45].
Regarding claim 14, Pangal et al. in combination with McNeil Jr. et al. teach the limitations with respect to claim 10.
Furthermore, Pangal et al. disclose wherein determining the programming time comprises:
detect that a block erase count,
determining whether the block erase count satisfies a threshold; and
determining the programming time based on whether the block erase count satisfies the threshold [see Fig. 4, if the current cycle count has reached a first cycle threshold (Cyc 1) or a failure trigger occurs (such as Block Fail Rate (BFR) threshold value or (e.g., near miss) ECC event), a second trim profile (e.g., profile B) is applied (e.g., by the controller logic 125) at an operation 406, para. 30].
Regarding claim 15, Pangal et al. in combination with McNeil Jr. et al. teach the limitations with respect to claim 14.
Furthermore, Pangal et al. disclose wherein determining the programming time comprises:
determining that the programming time is:
the first programming time if the block erase count does not satisfy the threshold, or the second programming time if the block erase count satisfies the threshold [see Fig. 4, at an operation 404, if the current cycle count has reached a first cycle threshold (Cyc 1) or a failure trigger occurs (such as Block Fail Rate (BFR) threshold value or (e.g., near miss) ECC event), a second trim profile (e.g., profile B) is applied (e.g., by the controller logic 125) at an operation 406. Otherwise, an operation 408 continues to use trim profile A, para. 30].
Regarding independent claim 17, Pangal et al. disclose an apparatus [Fig. 1: 100], comprising:
means for performing a first one or more write operations [Fig. 4: 402, a first trim profile (e.g., profile A) is applied (e.g., by the controller logic 125), para. 30] over which a voltage of a charge is incrementally increased or decreased for one or more cells of the memory device [the trim profiles may include TEV, R1, PV1, R2, PV2, R3, PV3, program start voltage (Vpgm), erase start voltage (Vera), and the unselected WL (Word Line) read voltage (Vread/Vpassr). The trims above may be decreased with cycles, except Vera which may be increased. Other trims above may be changed independently, para. 26 and 28],
means for detecting a trigger event [Fig. 4: 404, if the current cycle count has reached a first cycle threshold (Cyc 1) or a failure trigger occurs (such as Block Fail Rate (BFR) threshold value or (e.g., near miss) ECC event), para. 30];
means for performing a second one or more write operations [Fig. 4: 406, a second trim profile (e.g., profile B) is applied (e.g., by the controller logic 125)] based on detecting the trigger event.
However, Pangal et al. are silent with respect to perform first one or more write operations using a first amount of time for a programming time, and perform a second one or more write operations using a second amount of time for the programming time.
McNeil Jr. et al. teach a tPROG circuitry 112 can be configured to operate the quantity of logical units with one of a plurality of trims that correspond to the selected programming time. Each trim that corresponds to a particular programming time corresponds to a different performance target. The plurality of trims can be stored in a library of trims that are stored with correspondence to programming times, such as in a table or database. The tPROG circuitry 112 can select a trim from the library based on the selected programming time [para. 35]. The tPROG circuitry 112 can select a slowest one of the plurality of programming times that is sufficient to provide the required throughput. Some of the plurality of programming times are slower than a fastest programming time of the non-volatile memory device 116 [para. 32]. Moreover, McNeil Jr. et al. also disclose examples of trims include programming voltages, programming frequency, a program start voltage, a program step voltage, a program inhibit start voltage, and an erase verify voltage [para. 38].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of McNeil Jr. et al. to the teaching of Pangal et al. such that incorporating programming time (tPROG) circuitry of McNeil Jr. et al. that selects a trim from the library based on the selected programming time into Pangal et al.’s memory controller, thereby enabling the controller to perform earlier write operations (trim profile A) with one programming time and later write operations (trim profile B) with another programming time after a trigger event, with expected result of optimizing reliability and performance across life of memory device.
Regarding claim 19, Pangal et al. in combination with McNeil Jr. et al. teach the limitations with respect to claim 17.
Furthermore, McNeil Jr. et al. disclose wherein the means for detecting the trigger event comprises:
means for receiving, from a host device, a command indicating that the programming time is to be switched from the first amount of time to the second amount of time [see Fig. 2, plot 224 illustrates different methods of programming a memory device to store time based telemetric sensor data received from a host. Transitioning from method-A to method-B to method-C, slower programming times are used, which results in greater memory cell endurance, para. 43. A definition of the required throughput can be received from the host upon an initial connection to the host and the memory device can be operated with the selected programming time thereafter, para. 45].
Regarding claim 20, Pangal et al. in combination with McNeil Jr. et al. teach the limitations with respect to claim 17.
Furthermore, Pangal et al. disclose wherein the means for detecting the trigger event comprises:
means for detecting that a block erase count satisfies a threshold [the current cycle count has reached a first cycle threshold (Cyc 1) or a failure trigger occurs (such as Block Fail Rate (BFR) threshold value or (e.g., near miss) ECC event), para. 30].
Claims 4-5, 9, 11, 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Pangal et al. (US 20140082460) in view of McNeil Jr. et al. (US 20220050601) as applied to claims 1, 10 and 17 above, in view of Montierth et al. (US 8437189).
Regarding claim 4, Pangal et al. in combination with McNeil Jr. et al. teach the limitations with respect to claim 1.
However, Pangal et al. in combination with McNeil Jr. et al. are silent with respect to wherein the first one or more write operations are associated with writing original equipment manufacturer data or original design manufacturer data, and
wherein the second one or more write operations are associated with writing user data.
Montierth et al. teach wherein the first one or more write operations are associated with writing original equipment manufacturer data or original design manufacturer data [the high retention region may be used to store retained data. Retained data may be characterized as data that is to be retained for the life of the electronic assembly including, but not limited to, firmware code, program code, or network identification information, col. 7, lines 25-30], and
wherein the second one or more write operations are associated with writing user data [the low retention region may be used to store transient data, including but not limited to, print pages to be sent to a printing device, incoming and/or outgoing faxes, and Compact Disk (CD) buffering, col. 7, lines 31-43].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Montierth et al. to the teaching of Pangal et al. in combination with McNeil Jr. et al. such that the Pangal et al.’s trim profile A is used for writing data into the high retention region while the trim profile B is used for writing data into the low retention region as taught by Montierth et al. to reduce its retention time and increase additional memory without adding cost [see Montierth et al.’s col. 5, lines 1-2 and 26-31].
Regarding claim 5, Pangal et al. in combination with McNeil Jr. et al. and Montierth et al. teach the limitations with respect to claim 4.
Furthermore, McNeil Jr. et al. disclose wherein the first amount of time is greater than the second amount of time [some of the plurality of programming times are slower than a fastest programming time of the non-volatile memory device 116, para. 32].
Regarding claim 9, Pangal et al. in combination with McNeil Jr. et al. teach the limitations with respect to claim 8.
However, Pangal et al. in combination with McNeil Jr. et al. are silent with respect to wherein a value of the threshold is based on a data write size of data associated with the first one or more write operations.
Montierth et al. disclose wherein a value of the threshold is based on a data write size of data associated with the first one or more write operations [col. 7, lines 61-67, as well as col. 9, lines 32-33].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Montierth et al. to the teaching of Pangal et al. in combination with McNeil Jr. et al. such that a value of the threshold of Pangal et al. is based on a data write size of data associated with the first one or more write operations as taught by Montierth et al. to enhance data retention reliability and extend flash life time [see Montierth et al.’s col. 5, lines 1-2 and 14-25].
Regarding claim 11, Pangal et al. in combination with McNeil Jr. et al. teach the limitations with respect to claim 10.
Furthermore, McNeil Jr. et al. disclose wherein determining the programming time is based on a data type associated with the data [different methods of programming a memory device to store time based telemetric sensor data received from a host, para. 43].
However, Pangal et al. in combination with McNeil Jr. et al. are silent with respect to wherein the data type includes at least one of:
manufacturer data, or user data.
Montierth et al. teach wherein the data type includes at least one of:
manufacturer data [the high retention region may be used to store retained data. Retained data may be characterized as data that is to be retained for the life of the electronic assembly including, but not limited to, firmware code, program code, or network identification information, col. 7, lines 25-30], or user data [the low retention region may be used to store transient data, including but not limited to, print pages to be sent to a printing device, incoming and/or outgoing faxes, and Compact Disk (CD) buffering, col. 7, lines 31-43].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Montierth et al. to the teaching of Pangal et al. in combination with McNeil Jr. et al. such that determining the programming time is based on a data type associated with the data as taught by McNeil Jr. et al. wherein the data type includes at least one of manufacturer data, or user data as taught by Montierth et al. to reduce its retention time and increase additional memory without adding cost [see Montierth et al.’s col. 5, lines 1-2 and 26-31].
Regarding claim 16, Pangal et al. in combination with McNeil Jr. et al. teach the limitations with respect to claim 10.
Furthermore, McNeil Jr. et al. disclose determining the programming time [the tPROG circuitry 112 can select a trim from the library based on the selected programming time, para. 35].
However, Pangal et al. in combination with McNeil Jr. et al. are silent with respect to determining an operation phase associated with the memory device, wherein the operation phase includes a manufacturing phase or an end user phase.
Montierth et al. teach determining an operation phase associated with the memory device, wherein the operation phase includes a manufacturing phase [the high retention region may be used to store retained data. Retained data may be characterized as data that is to be retained for the life of the electronic assembly including, but not limited to, firmware code, program code, or network identification information, col. 7, lines 25-30] or an end user phase [the low retention region may be used to store transient data, including but not limited to, print pages to be sent to a printing device, incoming and/or outgoing faxes, and Compact Disk (CD) buffering, col. 7, lines 31-43].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Montierth et al. to the teaching of Pangal et al. in combination with McNeil Jr. et al. such that the Pangal et al.’s trim profile A is used for writing data into the high retention region while the trim profile B is used for writing data into the low retention region as taught by Montierth et al. to reduce its retention time and increase additional memory without adding cost [see Montierth et al.’s col. 5, lines 1-2 and 26-31].
Regarding claim 18, Pangal et al. in combination with McNeil Jr. et al. teach the limitations with respect to claim 17.
Furthermore, Pangal et al. disclose the first one or more write operation [trim profile A], the second one or more write operations [trim profile B]. Besides that, McNeil Jr. et al. disclose wherein the first amount of time is greater than the second amount of time [the tPROG circuitry 112 can select a trim from the library based on the selected programming time, para. 35. Some of the plurality of programming times are slower than a fastest programming time of the non-volatile memory device 116, para. 32].
However, Pangal et al. in combination with McNeil Jr. et al. are silent with respect to determine initialization data and user data.
Montierth et al. teach determining initialization data [the high retention region may be used to store retained data. Retained data may be characterized as data that is to be retained for the life of the electronic assembly including, but not limited to, firmware code, program code, or network identification information, col. 7, lines 25-30] or user data [the low retention region may be used to store transient data, including but not limited to, print pages to be sent to a printing device, incoming and/or outgoing faxes, and Compact Disk (CD) buffering, col. 7, lines 31-43].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Montierth et al. to the teaching of Pangal et al. in combination with McNeil Jr. et al. such that the Pangal et al.’s trim profile A is used for writing data into the high retention region while the trim profile B is used for writing data into the low retention region as taught by Montierth et al. to reduce its retention time and increase additional memory without adding cost [see Montierth et al.’s col. 5, lines 1-2 and 26-31].
Response to Arguments
Applicant’s arguments with respect to claims 1, 10 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825