Prosecution Insights
Last updated: April 19, 2026
Application No. 18/538,738

INTEGRATED CIRCUIT DEVICE INCLUDING THERMAL INTERPOSER LAYER

Non-Final OA §102
Filed
Dec 13, 2023
Examiner
ERDEM, FAZLI
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Qualcomm Incorporated
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
2y 7m
To Grant
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
895 granted / 1050 resolved
+17.2% vs TC avg
Strong +16% interview lift
Without
With
+15.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
32 currently pending
Career history
1082
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
48.4%
+8.4% vs TC avg
§102
39.1%
-0.9% vs TC avg
§112
7.4%
-32.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1050 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lan et al. (20230197554). Regarding Claim 1, in Fig. 3, Lan et al. discloses a device comprising: a die 310 including: a set of contacts 312 coupled to a first side of the die; and active circuitry 310 coupled to the set of contacts; a thermal interposer layer (TIL) 344 adjacent to the first side of the die, the TIL including a thermally conductive material having one or more though hole vias (THVs) aligned with one or more first contacts of the set of contacts; and a set of conductive connectors 332 that are coupled to the one or more first contacts and that extend through the THVs. Regarding Claim 2, a package substrate 350 including a second set of contacts, wherein one or more second contacts of the second set of contacts are coupled to the set of conductive connectors. Regarding Claim 3, in Lang et al., at least one THV of the one or more THVs has an oblong cross-section. Regarding Claim 4, in Lang et al, one conductive connector of the set of conductive connectors 332 corresponds to a non-circular thermal bar that extends through the at least one THV having the oblong cross-section. Regarding Claim 5, in Lang et al, at least one THV of the one or more THVs has a substantially circular cross-section. Regarding Claim 6, in Lang et al., in paragraph 0036, at least one of the set of conductive connectors includes copper. Regarding Claim 7, in Lang et al., in paragraphs 0032 and 035, the thermally conductive material includes alumina ceramic. Regarding Claim 8, in Lang et al, in paragraphs 0046 and 0048, the thermally conductive material includes aluminum nitride. Regarding Claim 9, in Lang et al, in paragraphs 0030 and 0031 the thermally conductive material includes silicon carbide (SiC). Regarding Claim 10, in Lang et al, in paragraphs 0031 and 0032, the die corresponds to a chiplet that is separated from a package substrate by the TIL. Regarding Claim 11, in paragraphs 0031 and 0032 of Lang et al, a second chiplet that is separated from the package substrate by a second TIL. Regarding Claim 12, in Lang et al, TIL dissipates heat from the die. Regarding Claim 13, in Lang et al,: a heat sink; and thermal interface material (TIM) adjacent to a second side of the die that is opposite the first side, wherein the TIM is between the heat sink and the die. Regarding Claim 14, in Lang et al, in paragraphs 0059, 0061 and 0062, a high-bandwidth memory (HBM) module including a set of second conductive connectors that extend through the HBM module and that are aligned with the set of conductive connectors. Regarding Claim 15, Lang discloses method of fabrication comprising: forming a thermal interposer layer (TIL) 344 including a thermally conductive material having one or more through hole vias (THVs); forming a set of conductive connectors 332 that are coupled to one or more first contacts of a die, the die including a set of contacts coupled to a first side of the die, wherein the die includes active circuitry coupled to the set of contacts, and wherein the set of contacts includes the one or more first contacts; and attaching the TIL to the die with the set of conductive connectors extending through the one or more THVs to couple to the one or more first contacts. Regarding Claim 16, in Lang, filling gaps between the set of conductive connectors and the thermally conductive material. Regarding Claim 17, in Lang, forming solder bumps 338 on the set of conductive connectors; and electrically connecting one or more second contacts of a package substrate to the solder bumps. Regarding Claim 18, in Lang, at least one THV of the one or more THVs has an oblong cross-section. Regarding Claim 19, in Lang, at least one conductive connector of the set of conductive connectors corresponds to a non-circular thermal bar that extends through the at least one THV having the oblong cross-section. Regarding Claim 20, in Lang, at least one THV of the one or more THVs has a substantially circular cross-section. Regarding Claim 21, in Lang, in paragraphs 0030.0035 and 0036, at least one of the set of conductive connectors includes copper. Regarding Claim 22, in paragraphs 0032 and 0035 of Lang, the thermally conductive material includes alumina ceramic. Regarding Claim 23, in Lang, the thermally conductive material includes aluminum nitride. Regarding Claim 24, in Lang, the thermally conductive material includes silicon carbide (SiC). Regarding Claim 25, in Lang, the die corresponds to a chiplet that is separated from a package substrate by the TIL. Regarding Claim 26, in Lang, wherein the TIL dissipates heat from the die. Regarding Claim 27, Lang disclose a device comprising: a first chiplet including: a first set of contacts coupled to a first side of the first chiplet; and first active circuitry coupled to the first set of contacts; a first thermal interposer layer (TIL) 344 adjacent to the first side of the first chiplet, the first TIL including first thermally conductive material having one or more first though hole vias (THVs) aligned with one or more first contacts of the first set of contacts; a first set of conductive connectors 332 that are coupled to the one or more first contacts and that extend through the first THVs; and a package substrate including a set of substrate contacts, one or more first substrate contacts of the set of substrate contacts coupled to the first set of conductive connectors. Regarding Claim 28, in paragraphs 0031 and 0032 of Lang it is disclosed a second chiplet including: a second set of contacts coupled to a second side of the second chiplet; and second active circuitry coupled to the second set of contacts; a second TIL adjacent to the second side of the second chiplet, the second TIL including second thermally conductive material having one or more second THVs aligned with one or more second contacts of the second set of contacts; and a second set of conductive connectors that are coupled to the one or more second contacts and that extend through the second THVs, one or more second substrate contacts of the set of substrate contacts coupled to the second set of conductive connectors. Regarding Claim 29, in Lang, a first THV of the one or more first THVs has an oblong cross-section. Regarding Claim 30, in Lang, a first conductive connector of the first set of conductive connectors corresponds to a non-circular thermal bar that extends through the first THV. Examiner is including Nakazawa (202217732) and Lee (20240136267) as pertinent prior art references that are not relied upon but that teach heat dissipation configurations. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FAZLI ERDEM/Primary Examiner, Art Unit 2812 2/4/2026
Read full office action

Prosecution Timeline

Dec 13, 2023
Application Filed
Nov 21, 2024
Response after Non-Final Action
Feb 04, 2026
Non-Final Rejection — §102
Mar 27, 2026
Interview Requested
Apr 02, 2026
Applicant Interview (Telephonic)
Apr 02, 2026
Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12593563
DISPLAY DEVICE
2y 5m to grant Granted Mar 31, 2026
Patent 12593631
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Mar 31, 2026
Patent 12588498
FINFET STRUCTURE WITH CONTROLLED AIR GAPS
2y 5m to grant Granted Mar 24, 2026
Patent 12581679
SPLIT-GATE POWER MOS DEVICE AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Mar 17, 2026
Patent 12581877
SELECTIVE DEPOSITION OF METAL OXIDES USING SILANES AS AN INHIBITOR
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+15.9%)
2y 7m
Median Time to Grant
Low
PTA Risk
Based on 1050 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month