Prosecution Insights
Last updated: May 29, 2026
Application No. 18/538,738

INTEGRATED CIRCUIT DEVICE INCLUDING THERMAL INTERPOSER LAYER

Non-Final OA §103
Filed
Dec 13, 2023
Examiner
ERDEM, FAZLI
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Qualcomm Incorporated
OA Round
2 (Non-Final)
85%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
907 granted / 1062 resolved
+17.4% vs TC avg
Strong +16% interview lift
Without
With
+15.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
28 currently pending
Career history
1089
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
62.5%
+22.5% vs TC avg
§102
30.7%
-9.3% vs TC avg
§112
3.7%
-36.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1062 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to claims 1-30 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lan et al. (20230197554) in view of Horiuchi et al. (20010026010) Regarding Claim 1, in Fig. 3, Lan et al. discloses a device comprising: a die 310 including: a set of contacts 312 coupled to a first side of the die; and active circuitry 310 coupled to the set of contacts; a thermal interposer layer (TIL) 344 adjacent to the first side of the die, the TIL including a thermally conductive material having one or more though hole vias (THVs) aligned with one or more first contacts of the set of contacts; and a set of conductive connectors 332 that are coupled to the one or more first contacts and that extend through the THVs. Lan et al. fails to disclose the newly added limitation of first thermal interface material (TIM) filling gaps between the set of conductive connectors and the thermally conductive material of the TIL. However, Horiuchi discloses a semiconductor packaging structure where the required limitation is disclosed in paragraphs 0086 and 0091 and in Figs. 4-10 as elements 21/29/30 (please compare the paragraph 0049 of the instant application as published (20250201662) to paragraphs 0086 and 0091 of Horiuchi in terms of materials) It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required filling material in Lan et al. as taught by Horiuchi et al in order to have thermal conduction/dissipation through the matching materials. (i.e. the materials of the instant application and Horiuchi match to each other) Regarding Claim 2, in Lan et al., a package substrate 350 including a second set of contacts, wherein one or more second contacts of the second set of contacts are coupled to the set of conductive connectors. Regarding Claim 3, in Lan et al., in Lan et al., at least one THV of the one or more THVs has an oblong cross-section. Regarding Claim 4, in Lan et al., in Lan et al, one conductive connector of the set of conductive connectors 332 corresponds to a non-circular thermal bar that extends through the at least one THV having the oblong cross-section. Regarding Claim 5, in Lan et al, at least one THV of the one or more THVs has a substantially circular cross-section. Regarding Claim 6, in Lan et al., in paragraph 0036, at least one of the set of conductive connectors includes copper. Further see paragraphs 0086 and 0091 of Horiuchi for materials. Regarding Claim 7, in Lan et al., in paragraphs 0032 and 035, the thermally conductive material includes alumina ceramic. Regarding Claim 8, in Lan et al, in paragraphs 0046 and 0048, the thermally conductive material includes aluminum nitride. Regarding Claim 9, in Lan et al, in paragraphs 0030 and 0031 the thermally conductive material includes silicon carbide (SiC). Regarding Claim 10, in Lan et al, in paragraphs 0031 and 0032, the die corresponds to a chiplet that is separated from a package substrate by the TIL. Regarding Claim 11, in paragraphs 0031 and 0032 of Lan et al, a second chiplet that is separated from the package substrate by a second TIL. Regarding Claim 12, in Lan et al, TIL dissipates heat from the die. Regarding Claim 13, in Lan et al,: a heat sink; and thermal interface material (TIM) adjacent to a second side of the die that is opposite the first side, wherein the second TIM is between the heat sink and the die. Regarding Claim 14, in Lan et al, in paragraphs 0059, 0061 and 0062, a high-bandwidth memory (HBM) module including a set of second conductive connectors that extend through the HBM module and that are aligned with the set of conductive connectors. Regarding Claim 15, Lan discloses method of fabrication comprising: forming a thermal interposer layer (TIL) 344 including a thermally conductive material having one or more through hole vias (THVs); forming a set of conductive connectors 332 that are coupled to one or more first contacts of a die, the die including a set of contacts coupled to a first side of the die, wherein the die includes active circuitry coupled to the set of contacts, and wherein the set of contacts includes the one or more first contacts; and attaching the TIL to the die with the set of conductive connectors extending through the one or more THVs to couple to the one or more first contacts. Lan et al. fails to disclose the newly added limitation of first thermal interface material (TIM) filling gaps between the set of conductive connectors and the thermally conductive material of the TIL. However, Horiuchi discloses a semiconductor packaging structure where the required limitation is disclosed in paragraphs 0086 and 0091 and in Figs. 4-10 as elements 21/29/30 (please compare the paragraph 0049 of the instant application as published (20250201662) to paragraphs 0086 and 0091 of Horiuchi in terms of materials) It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required filling material in Lan et al. as taught by Horiuchi et al in order to have thermal conduction/dissipation through the matching materials. (i.e. the materials of the instant application and Horiuchi match to each other) Regarding Claim 16, in Lan, filling gaps between the set of conductive connectors and the thermally conductive material. Regarding Claim 17, in Lan, forming solder bumps 338 on the set of conductive connectors; and electrically connecting one or more second contacts of a package substrate to the solder bumps. Regarding Claim 18, in Lan, at least one THV of the one or more THVs has an oblong cross-section. Regarding Claim 19, in Lan, at least one conductive connector of the set of conductive connectors corresponds to a non-circular thermal bar that extends through the at least one THV having the oblong cross-section. Regarding Claim 20, in Lan, at least one THV of the one or more THVs has a substantially circular cross-section. Regarding Claim 21, in Lan, in paragraphs 0030.0035 and 0036, at least one of the set of conductive connectors includes copper. Regarding Claim 22, in paragraphs 0032 and 0035 of Lan, the thermally conductive material includes alumina ceramic. Regarding Claim 23, in Lan, the thermally conductive material includes aluminum nitride. Regarding Claim 24, in Lan, the thermally conductive material includes silicon carbide (SiC). Regarding Claim 25, in Lan, the die corresponds to a chiplet that is separated from a package substrate by the TIL. Regarding Claim 26, in Lan, wherein the TIL dissipates heat from the die. Regarding Claim 27, Lan disclose a device comprising: a first chiplet including: a first set of contacts coupled to a first side of the first chiplet; and first active circuitry coupled to the first set of contacts; a first thermal interposer layer (TIL) 344 adjacent to the first side of the first chiplet, the first TIL including first thermally conductive material having one or more first though hole vias (THVs) aligned with one or more first contacts of the first set of contacts; a first set of conductive connectors 332 that are coupled to the one or more first contacts and that extend through the first THVs; and a package substrate including a set of substrate contacts, one or more first substrate contacts of the set of substrate contacts coupled to the first set of conductive connectors. Lan et al. fails to disclose the newly added limitation of first thermal interface material (TIM) filling gaps between the set of conductive connectors and the thermally conductive material of the TIL. However, Horiuchi discloses a semiconductor packaging structure where the required limitation is disclosed in paragraphs 0086 and 0091 and in Figs. 4-10 as elements 21/29/30 (please compare the paragraph 0049 of the instant application as published (20250201662) to paragraphs 0086 and 0091 of Horiuchi in terms of materials) It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required filling material in Lan et al. as taught by Horiuchi et al in order to have thermal conduction/dissipation through the matching materials. (i.e. the materials of the instant application and Horiuchi match to each other) Regarding Claim 28, in paragraphs 0031 and 0032 of Lan it is disclosed a second chiplet including: a second set of contacts coupled to a second side of the second chiplet; and second active circuitry coupled to the second set of contacts; a second TIL adjacent to the second side of the second chiplet, the second TIL including second thermally conductive material having one or more second THVs aligned with one or more second contacts of the second set of contacts; and a second set of conductive connectors that are coupled to the one or more second contacts and that extend through the second THVs, one or more second substrate contacts of the set of substrate contacts coupled to the second set of conductive connectors. Regarding Claim 29, in Lan, a first THV of the one or more first THVs has an oblong cross-section. Regarding Claim 30, in Lan, a first conductive connector of the first set of conductive connectors corresponds to a non-circular thermal bar that extends through the first THV. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FAZLI ERDEM/Primary Examiner, Art Unit 2812 4/30/2026
Read full office action

Prosecution Timeline

Dec 13, 2023
Application Filed
Nov 21, 2024
Response after Non-Final Action
Feb 06, 2026
Non-Final Rejection mailed — §103
Mar 27, 2026
Interview Requested
Apr 02, 2026
Examiner Interview Summary
Apr 02, 2026
Applicant Interview (Telephonic)
Apr 20, 2026
Response Filed
Apr 30, 2026
Final Rejection (signed) — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+15.8%)
2y 5m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1062 resolved cases by this examiner. Grant probability derived from career allowance rate.

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