DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Group II and Species B in the reply filed on 9 March 2026 is acknowledged. Claims 1-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group I, there being no allowable generic or linking claim. Applicants are reminded to indicate the withdrawn status of claims 1-10 in their next submission of a claim listing.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 11, 12, and 15-19 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Ryu et al. (US20210143160A1).
Regarding claim 11, Ryu teaches in Fig. 4A/5A a semiconductor structure, comprising:
a stack structure (GS) having a first surface (upper surface of GS) {[0039]};
a channel structure (CH) extending through the stack structure (GS) in a stacking direction (z direction), and comprising a channel layer (140) and a plug structure (148) electrically connected with the channel layer (140), wherein the plug structure (148) is located close to the first surface (upper surface of GS) {[0039, 0047]};
a protruding structure (P1) located on the plug structure (148) protruding above the first surface (upper surface of GS) away from the plug structure (148) {[0060]};
an upper select gate layer (150) located on the first surface (upper surface of GS) of the stack structure (GS) and covering the protruding structure (P1) {[0039]}; and
an upper select channel structure (SCH) extending through the upper select gate layer (150) and the protruding structure (P1) in the stacking direction (z direction), and being in contact with the plug structure (148) {[0039]}.
Regarding claim 12, Ryu teaches the semiconductor structure of claim 11, and Ryu further teaches in Fig. 4A wherein the upper select gate layer (150) comprises a recessed region (region encompassing through-hole region 150H through which upper select channel structure SCH passes) corresponding (vertically above upper select channel structure SCH for electrical interconnection of P1 and SCH) to a position of the protruding structure (P1).
Regarding claim 15, Ryu teaches the semiconductor structure of claim 11, and Ryu further teaches wherein the upper select channel structure (SCH) comprises:
a conductive layer (160) {[0058]}; and
an insulating layer (170a) surrounding the conductive layer (160) {[0039],
wherein an angle between a surface of the upper select gate layer (150) close (both the lower and upper surfaces of 150 are close to P1) to the protruding structure (P1) and the insulating layer (170a) in the upper select gate layer (150) is not less than 90° {Figs. 4A/5A, 10G}.
Regarding claim 16, Ryu teaches the semiconductor structure of claim 15, and Ryu further teaches wherein the conductive layer (160) extends through the upper select gate layer (150), the insulating layer (170a), and the protruding structure (P1) in the stacking direction (z direction), and is in contact with the plug structure (148).
Regarding claim 17, Ryu teaches the semiconductor structure of claim 11, and Ryu further teaches wherein the channel structure (CH) further comprises:
a memory functional layer (145) {[0047]}; and
a filling layer (146) {[0047]};
wherein the channel layer (140) surrounds the filling layer (146), and the memory functional layer (145) surrounds the channel layer (140) {[0047]}.
Regarding claim 18, Ryu teaches in Fig. 4A/5A a memory system, comprising:
a memory device (20) {Fig. 1; [0026]}, comprising:
a stack structure (GS) having a first surface (upper surface of GS) {[0039]};
a channel structure (CH) extending through the stack structure (GS) in a stacking direction (z direction), and comprising a channel layer (140) and a plug structure (148) electrically connected with the channel layer (140), wherein the plug structure (148) is located close to the first surface (upper surface of GS) {[0039, 0047]};
a protruding structure (P1) located on the plug structure (148) protruding above the first surface (upper surface of GS) away from the plug structure (148) {[0060]};
an upper select gate layer (150) located on the first surface (upper surface of GS) of the stack structure (GS) and covering the protruding structure (P1) {[0039]}; and
an upper select channel structure (SCH) extending through the upper select gate layer (150) and the protruding structure (P1) in the stacking direction (z direction), and being in contact with the plug structure (148) {[0039]}; and
a controller (36) coupled with the memory device (20) and configured to control the memory device (20) to store data {Fig. 1; [0026]}.
Regarding claim 19, Ryu teaches the memory system of claim 18, and Ryu further teaches in Fig. 4A wherein the upper select gate layer (150) comprises a recessed region (region encompassing through-hole region 150H through which upper select channel structure SCH passes) corresponding (vertically above upper select channel structure SCH for electrical interconnection of P1 and SCH) to a position of the protruding structure (P1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13, 14, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryu as applied to claim 1 (for claims 13 and 14) and claim 18 (for claim 20) above, and further in view of He (CN115440672A) (English translation enclosed).
Regarding claim 13, Ryu teaches the semiconductor structure of claim 12, but Ryu does not teach further comprising: an etch stop layer between the protruding structure and the upper select gate layer.
In an analogous art, He teaches in Fig. 5j and paragraph [0089] an etch stop layer (241) between a protruding structure (portion of 271 above 241 {Fig. 5j}) and an upper select gate layer (242) {Figs. 5f, 5g; [0089], layer (241) has a lower etch rate than layer (231) and, thus, acts as an etch stop}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ryu’s semiconductor structure based on the teachings of He – to include an etch stop layer between the protruding structure and the upper select gate layer – so a sacrificial part may be removed by etching without removing layers protected by the etch stop layer. He [0089].
Regarding claim 14, Ryu teaches the semiconductor structure of claim 13, but Ryu does not teach wherein the etch stop layer comprises: a recess portion in contact with the protruding structure; and a protrude portion in contact with the recessed region of the upper select gate layer.
He teaches in Fig. 5j that an etch stop layer (241) has a through-hole region (250; Fig. 5h) through which a protruding structure (271) passes. The etch stop layer (241) has a recess portion (portion of 241 through which protruding structure 271 passes) in contact with a protruding structure (271). Additionally, the etch stop layer (241) has a protrude portion (all of 241 not directly covered by 242, which may include some or all of the recess portion identified immediately above) in contact with a recessed region (region encompassing entirety of the through-hole 250 passing through 242) of the upper select gate layer (242). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ryu’s semiconductor structure as modified by He based on the further teachings of He – to include the features identified immediately above – so Ryu’s channel structure may be electrically connected to a memory bit line through the intermediate plug structure and protruding structure. He [0092].
Regarding claim 20, Ryu teaches the memory system of claim 19, but Ryu does not teach further comprising:
an etch stop layer between the protruding structure and the upper select gate layer, the etch stop layer comprises:
a recess portion in contact with the protruding structure; and
a protrude portion in contact with the recessed region of the upper select gate layer.
He teaches in Fig. 5j an etch stop layer (241) between the protruding structure (portion of 271 above 241 {Fig. 5j}) and the upper select gate layer (242) {Figs. 5f, 5g; [0089], layer (241) has a lower etch rate than layer (231) and, thus, acts as an etch stop}, the etch stop layer (241) comprises: a recess portion (portion of 241 through which protruding structure 271 passes) in contact with a protruding structure (271); and a protrude portion (all of 241 not directly covered by 242, which may include some or all of the recess portion identified immediately above) in contact with a recessed region (region encompassing entirety of the through-hole 250 passing through 242) of the upper select gate layer (242). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ryu’s memory system based on the teachings of He – to include the features identified immediately above – so Ryu’s channel structure may be electrically connected to a memory bit line through the intermediate plug structure and protruding structure. He [0092].
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Simsek-Ege et al. (US20140339621A1) teaches methods for forming a string of memory cells. One such string of memory cells can be formed at least partially in a stack of materials comprising a plurality of alternating levels of control gate material and insulator material. A memory cell of the string can include floating gate material adjacent to a level of control gate material of the levels of control gate material. The memory cell can also include tunnel dielectric material adjacent to the floating gate material. The level of control gate material and the tunnel dielectric material are adjacent opposing surfaces of the floating gate material. The memory cell can include metal along an interface between the tunnel dielectric material and the floating gate material. The memory cell can further include a semiconductor material adjacent to the tunnel dielectric material.
Conclusion
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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