Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Title The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01). This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc. The following title is suggested: “ Method for forming a semiconductor device with Vertical ly Stacked Transistor Contacts ” Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claim s 5 and 10-17 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Regarding claim 5 , the claim 4 recites a “first hardmask layer” and a “second hardmask layer”. Claim 5 states they are the “ same hardmask layer”. If they are the same physical layer. The “first” and “second” labels in the claim 4 are technically misaligned . Because it is unsure ‘are they deposited twice?’ or ‘is it re-patterned?’. Thus, creates interpretive ambiguity. Thus, the examiner recommends amending the limitation to “the first and second hardmak layers comprise a same physical layer ”. Regarding claim 1 0 , the claim recites the limitation “a third bottom S/D contact” in line(s) 11, but very next clause, it refers to “the third S/D bottom contact” (swapping word order). This creates ambiguity as to whether it is the same element. Thus, the examiner recommends amending the limitation to “ the third bottom S/D [[bottom]] contact ”. Regarding claims 11 - 17 , because of their dependency on claim 1 0 , these claims are also rejected for the reasons set forth above with respect to claim 1 0 . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim 1 is rejected under 35 U.S.C. 102 (a)( 1 ) and (a)(2) as being anticipated by Yang (US 20220093593 ; in the IDS on 12/13/23 ). Regarding claim 1. Yang discloses A method for forming a semiconductor device, comprising: forming, over a substrate 10 , a stacked transistor structure comprising: a bottom channel structure (14A region) and a top channel structure (16A region) stacked on top of the bottom channel structure (Fig 5) , a gate structure 24 extending across the bottom and top channel structures (Fig 5) , a first 34 B and a second 34 A bottom source/drain (S/D) structure on the bottom channel structure (Fig 8) , and a first 44 B and a second 44 A top S/D structure on the top channel structure (Fig 10) , wherein the first bottom and the first top S/D structures are formed at a first side (Fig 10: right side) , of the gate structure and the second bottom and the second top S/D structures are formed at a second side (Fig 10: left side) of the gate structure opposite the first side; forming a first 36 (right) ([0036]: metal silicide layer ) and a second 36 (left) bottom S/D contact on the first and the second bottom S/D structures (Fig 9) , respectively; forming a contact isolation layer 42 [0029]: dielectric layer) capping the first and second bottom S/D contacts to form capped first and second bottom S/D contacts (Fig 10) , and covering the capped first and second bottom S/D contacts with an interlayer dielectric layer 5 4 (Fig 11 , [0031] ) ; forming, at the first side of the gate structure, a first contact trench (the trench prior to forming CT 3 ) exposing the first top S/D structure over the capped first bottom S/D contact (Fig 13) ; forming, at the second side of the gate structure, a second contact trench (the trench prior to forming CT1) exposing the second bottom S/D contact and the second top S/D structure (Fig 13) ; and forming a first top S/D contact (CT3) in the first contact trench, in contact with the first top S/D structure, over the capped first bottom S/D contact (Fig 13) , and a second top S/D contact (CT1) in the second contact trench, in contact with the second top S/D structure and the second bottom S/D contact (Fig 13, [0025]: “ CT1 penetrates through the third source/drain structure 44A in the first direction D1. The first source/drain structure 34A is electrically connected with the third source/drain structure 44A via the contact structure CT1, and a part of the first source/drain structure 34A ”) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2 -4 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20220093593 ; in the IDS on 12/13/23) in view of Lee (US 20190131395 ) . Regarding claim 2. Yang discloses The method according to claim 1 . But Yang does not specifically disclose wherein the first contact trench is formed while masking the interlayer dielectric layer at the second side of the gate structure, and wherein the second contact trench is formed subsequent to the first contact trench, while masking the first contact trench and the interlayer dielectric layer at the first side of the gate structure. However, Lee discloses each contact 40 and 36 are formed by separate lithography and etching process ([0076]: “ The contact openings can be formed by lithography and etching. The first S/D contact structures 36 ”, and then [0080]: “ S/D contact structure 40 is then formed in the physically exposed first contact opening and on the additional dielectric material ” . Thus, Lee discloses the limitation). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Yang’s method to have the Lee’s method for the purpose of preventing damage or unintended etching of existing contact features during subsequent contact formation. Regarding claim 3. Yang discloses The method according to claim 1 . But Yang does not explicitly disclose wherein the first contact trench is formed using a first lithography and etching process and the second contact trench is formed using a second lithography and etching process. However, Lee discloses the first contact trench (Fig 13: prior to forming 40) is formed using a first lithography and etching process and the second contact trench (Fig 13: prior to forming 36) is formed using a second lithography and etching process ([0076]: “ The contact openings can be formed by lithography and etching. The first S/D contact structures 36 ” and then [0080]: “ S/D contact structure 40 is then formed in the physically exposed first contact opening and on the additional dielectric material ” . Thus, Lee discloses two different lithography and etching process ). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Yang’s method to have the Lee’s method for the purpose of providing precise, high-aspect-ratio, and high-density via structures, thereby, enhancing transistor performance by improving electrical contact areas and reducing resistance . Regarding claim 4. Yang in view of Lee discloses The method according to claim 3, Lee further discloses wherein the first lithography and etching process comprises patterning a first contact opening in a first hardmask layer formed over the stacked transistor structure, and opening the interlayer dielectric layer by etching via the first contact opening ([0076]: Lee discloses “ contact openings can be formed by lithography and etching ”, which means forming contact openings via lithography and etching fundamentally involves using a patterned hardmask layer to define the precise location and size of the opening, which is then etched into the underlying insulating dielectric layer. This process provides high selectivity, enabling the transfer of small features from a photoresist mask to a durable mask layer, preventing excessive photoresist erosion during deep etching ) , and Lee further discloses wherein the second lithography and etching process comprises patterning a second contact opening in a second hardmask layer formed over the stacked transistor structure, and opening the interlayer dielectric layer and the contact isolation layer of the capped second bottom S/D contact by etching via the second contact opening [0078] -[ 0079]. Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20220093593 ; in the IDS on 12/13/23) in view of Lee (US 20190131395 ), and further in view of Smith (US 20190288004 ; in the IDS on 12/13/23 ) . Regarding claim 5. Yang in view of Lee discloses The method according to claim 4 except wherein the first hardmask layer and the second hardmask layer is a same hardmask layer. However, Smith discloses a same hardmask layer 150 (Fig 1 9A-Fig 1 0A, [009 1 ] -[ 0092]) is used for lithography and etching process to form contact vias in trenches. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the Smith’s method within the Yang in view of Lee’s method for the purpose of providing enhancing lithography overlay margins, reduc ing photoresist erosion during deep dielectric etching, and ensur ing precise, vertical profiles with high aspect ratios. Regarding claim 6. Yang in view of Lee and Smith discloses The method according to claim 1, Smith discloses wherein forming the first and second top S/D contacts comprises simultaneously depositing one or more metals in the first and the second contact trenches (Fig 10B, [0094]) . Claims 7- 9 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20220093593 ; in the IDS on 12/13/23) in view of Shin (US 20100200926 ) . Regarding claim 7. Yang discloses The method according to claim 1 . But Yang does not explicitly disclose wherein forming the second contact trench comprises: opening the interlayer dielectric layer using an anisotropic etching process to expose the contact isolation layer of the capped second bottom S/D contact, and thereafter etching the contact isolation layer using an isotropic etching process, wherein the isotropic etching process removes a contact isolation layer portion remaining underneath the second top S/D structure after opening the interlayer dielectric layer. However, the claimed etching process is well known in the art. For example, S hin discloses opening the interlayer dielectric layer using an anisotropic etching process to expose the contact isolation layer of the capped second bottom S/D contact, and thereafter etching the contact isolation layer using an isotropic etching process, wherein the isotropic etching process removes a contact isolation layer portion remaining underneath the second top S/D structure after opening the interlayer dielectric layer (Fig 13 , [00 5 4]: Shin discloses preliminary contact hole 174 formation by anisotropic etching . And then Fig 1 4 , [00 55 ]: Shin discloses subsequent isotropic etch ing ) . Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Yang’s method to have the Shin’s two steps of etching process for the purpose of providing precise, deep, vertical, and high-aspect-ratio features with smooth profiles. The anisotropic step (e.g., RIE) defines the narrow, vertical sidewalls, while the subsequent isotropic step removes damage and rounds corners to reduce stress. Regarding claim 8. Yang in view of Shin discloses The method according to claim 7, Shin discloses wherein the anisotropic etching process is stopped on the contact isolation layer or on the second bottom S/D contact (Fig 13, [0054]) . Regarding claim 9. Yang in view of Shin discloses The method according to claim 8, Shin discloses wherein the isotropic etching process further removes an interlayer dielectric layer portion remaining underneath the second top S/D structure after opening the interlayer dielectric layer [0055] . Allowable Subject Matter Claims 10-17 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 1 0 . the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “ forming a non-stacked transistor structure comprising: a channel structure located at a same level over the substrate as the bottom channel structure of the stacked transistor structure, a further gate structure extending across the channel structure, and a first and a second S/D structure on the channel structure, the first S/D structure is formed at a first side of the further gate structure, and the second S/D structure is formed at a second side of the further gate structure opposite the first side of the further gate structure and merges with the second bottom S/D structure of the stacked transistor structure; forming a third bottom S/D contact on the first S/D structure of the non-stacked transistor structure; forming the contact isolation layer to cap the third S/D bottom contact to form a third capped bottom S/D contact, and covering the third capped bottom S/D contact with the interlayer dielectric layer; and forming the second bottom S/D contact on the second S/D structure of the non-stacked transistor structure ”. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT Changhyun Yi whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-7799 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday: 8A-4P . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Davienne Monbleau can be reached on FILLIN "SPE Phone?" \* MERGEFORMAT 571-272-1945 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Changhyun Yi/ Primary Examiner, Art Unit 2812