Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 14-18 in the reply filed on May 11, 2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 15, 2024 is in compliance with time for filing requirements of 37 C.F.R. 1.97, and thus, the information disclosure statement has been considered except as otherwise indicated.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Fill Trenches in a Semiconductor Substrate.
The abstract of the disclosure is objected to because it requires an update to reflect the current claimed invention. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The disclosure is objected to because of the following informalities: Requires an update to reflect the current claimed invention.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 14-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Batra et al. (US20060043455A1).
Regarding Claim 14:
Batra discloses a semiconductor device (semiconductor memory device; Fig. 1A-H, paragraph 21), comprising:
a substrate (element 105) having a plurality of trenches (elements 130 and 125, respectively) in a periphery area (element Periphery) and an array area (element Array) of the substrate, wherein an aspect ratio of a width to a depth of the trenches in the periphery area is in a range from 1.25 to 1.5;
a first oxide layer (Fig. 1C element 135) disposed on inner surfaces of the trenches of the substrate; and
a second oxide layer disposed (Fig. 1F element 140) on the first oxide layer, so that the trenches are filled, wherein a material of the first oxide layer and a material of the second oxide layer are identical (paragraphs 25 and 31), and wherein an aspect ratio of the trenches in the array area and the aspect ratio of the trenches in the periphery area are different (paragraphs 12-13, 26, and 31).
Regarding Claim 15:
Batra discloses a semiconductor device (semiconductor memory device; Fig. 1A-H, paragraph 21) according to claim 14, wherein the first oxide layer fully fills the trenches in the array area (Figs. 1C-E elements 135, 125 and Array, paragraph 26).
Regarding Claim 16:
Batra discloses a semiconductor device (semiconductor memory device; Fig. 1A-H, paragraph 21) according to claim 15, wherein the first oxide layer fully fills the trenches in the array area but does not fill the trenches in the periphery area (Figs. 1D-E elements 135, 125, and 130, paragraph 26).
Regarding Claim 17:
Batra discloses a semiconductor device (semiconductor memory device; Fig. 1A-H, paragraph 21) according to claim 16, wherein the first oxide layer and the second oxide layer fully fill the trenches in the periphery area (Fig. 1F elements 135, 140, and 130, paragraph 31).
Regarding Claim 18:
Batra discloses a semiconductor device (semiconductor memory device; Fig. 1A-H, paragraph 21) according to claim 14, wherein the aspect ratio of a width to a depth of the trenches in the array area is less than the aspect ratio of the width to the depth of the trenches in the periphery area (paragraphs 12-13, 26, 28 and 31).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Batra et al. (US20060043455A1).
Regarding Claim 14:
The examiner first notes that Batra does not explicitly disclose a specific range for an aspect ratio of the trenches in the periphery area. The examiner next notes that the aspect ratio of a width to a depth is a result effective variable because adjusting the ratio can lead to resistance variation and affect the breakdown voltage. The examiner additionally notes that the aspect ratio of the trench is recognized by the prior art as a result-effective variable (Batra, paragraphs 8 and 11). The examiner now notes that optimization of result effective variables through routine experimentation is an obviousness expedient and not a patentable distinction. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the semiconductor device described in Batra to include an aspect ratio of a width to a depth of the trenches in the periphery area to be in a range of 1.25 to 1.5. Doing so allows for the minimization of semiconductor devices without sacrificing the integrity of the trenches (Batra, paragraphs 7-9).
Regarding Claim 18:
The examiner first notes that Batra does not explicitly disclose the aspect ratio of the trenches in the array area to be less than the aspect ratio of the trenches in the periphery area. The examiner next notes that the aspect ratio of a width to a depth is a result effective variable because adjusting the ratio can lead to resistance variation and affect the breakdown voltage. The examiner additionally notes that the aspect ratios of the trenches in the array and periphery areas is recognized by the prior art as a result-effective variable (Batra, paragraphs 8 and 26). The examiner now notes that optimization of result effective variables through routine experimentation is an obviousness expedient and not a patentable distinction. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Citation of Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al.), Enda et al. (US 20180358257 A1), Park et al. (US 20170012098 A1), Kim et al. (US 20150162237 A1), Heo et al. (US 20030030121 A1), Chuang et al. (TW 202401658 A), Huang et al. (US 11315869 B1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Chloë E Benton whose telephone number is (571)272-9976. The examiner can normally be reached Monday-Thursday: 8am-6pm EST.
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/Chloë E Benton/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899