DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4-5, 7-8, and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20210098284 A1; hereinafter Park) in view of Venugopal et al. (US 20190206793 A1; hereinafter Venugopal), and further in view of Bonilla et al. (US 20130302978 A1; hereinafter Bonilla).
Regarding claim 1, FIGS. 8-10 of Park teach an interconnect structure (e.g. FIG. 10) comprising: a top via structure (104, 802) comprising a via (802 ¶ [0032]) located on a line (104 ¶ [0020]); an upper line structure (1002 ¶ [0034]) located on top of the via (802) and orientated perpendicular to the line of the top via structure (104, see FIG. 8).
Park does not teach a first two dimensional (2D) material layer located along sidewalls of the top via structure and on a topmost surface of the line of the top via structure; and a second 2D material layer located along sidewalls and a topmost surface of the upper line structure, wherein the first 2D material layer and the second 2D material layer contact each other along the sidewalls of the top via structure and the upper line structure.
FIGS. 3A-3D of Venugopal teach an interconnect structure (e.g. FIG. 3A) comprising: a top via structure (320, 330) comprising a via (330) located on a line (320 ¶ [0043]); an upper line structure (340) located on top of the via (330 ¶ [0043]); a first graphene material layer (first instance of 350 ¶ [0021]) located along sidewalls of the top via structure (e.g. sidewalls of 330) and on a topmost surface of the line of the top via structure (topmost surface of 320); and a second graphene material layer (second instance of 350 ¶ [0021]) located along sidewalls and a topmost surface of the upper line structure (sidewalls and topmost surface of 340, see FIG. 3D), wherein the first graphene material layer (first instance of 350) and the second graphene material layer (second instance of 350) contact each other along the sidewalls of the top via structure (e.g. sidewalls of 330) and the upper line structure (340, see FIGS. 3A & 3D).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the interconnect structure taught by Park with the graphene microlattices taught by Venugopal for the purpose of relieving stress during device operation and/or annealing (¶ [0021],[0043]).
Park as modified does not explicitly teach wherein the first and second graphene material layers are two-dimensional material layers.
FIG. 12 of Bonilla teaches a conductive layer (28’) and a two-dimensional (2D) material layer (24’) located along sidewalls and a topmost surface of the conductive layer (28’ ¶ [0058]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the interconnect structure taught by Park with the 2D graphene structure taught by Bonilla for the purpose of improving electromigration resistance (¶ [0024]) and providing a diffusion barrier/capping layer with high conductivity (¶ [0047]) and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Regarding claim 2, Park as modified teaches the interconnect structure of Claim 1, and FIGS. 7 and 10 of Park further teach wherein the upper line structure (1002) is aligned to the via of the top via structure (802 ¶ [0005]).
Regarding claim 4, Park as modified teaches the interconnect structure of Claim 1, and Bonilla further teaches wherein each of the first 2D material layer (first instance of 350 of Venugopal) and the second 2D material layer (second instance of 350 of Venugopal) comprises an electrically conductive material (e.g. graphene ¶ [0047],[0058]).
Regarding claim 5, Park as modified teaches the interconnect structure of Claim 4, and Bonilla further teaches wherein the first 2D material layer (first instance of 350 of Venugopal) is composed of a 2D material (e.g. graphene) that is compositionally the same as a 2D material (e.g. graphene) that provides the second 2D material layer (second instance of 350 of Venugopal ¶ [0058]).
Regarding claim 7, Park as modified teaches the interconnect structure of Claim 4, and Bonilla further teaches wherein the first 2D material layer (first instance of 350 of Venugopal) and the second 2D material layer (second instance of 350 of Venugopal) are composed of graphene, TaS2, MoS2, or WSe2 (e.g. graphene ¶ [0058]).
Regarding claim 8, Park as modified teaches the interconnect structure of Claim 1, and Park further teaches wherein each of the top via structure (104, 802) and the upper line structure (1002) is composed of an electrically conductive metal or an electrically conductive metal alloy (¶ [0021],[0034]-[0035]).
Regarding claim 12, Park as modified teaches the interconnect structure of Claim 1, FIG. 10 of Park further teaches further comprising a line structure (other instance of 104) located adjacent to the line of the top via structure (instance of 104).
Park does not teach wherein the line structure is covered with the first 2D material layer.
FIGS. 3A-3D of Venugopal teach a line structure (320 ¶ [0043]); wherein the line structure (320) is covered with the first graphene material layer (first instance of 350 ¶ [0021]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the interconnect structure taught by Park with the line structure taught by Venugopal for the purpose of relieving stress during device operation and/or annealing (¶ [0021],[0043]).
Park as modified does not explicitly teach wherein the first 2D material layer is a two-dimensional material layer.
FIG. 12 of Bonilla teaches a conductive layer (28’) and a two-dimensional (2D) material layer (24’) located along sidewalls and a topmost surface of the conductive layer (28’ ¶ [0058]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the interconnect structure taught by Park with the 2D graphene structure taught by Bonilla since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Regarding claim 13, Park as modified teaches the interconnect structure of Claim 1, and FIG. 5 of Venugopal further teaches a front-end-of-the-line (FEOL) level (level of 300 including transistors) and a metal level (level of 300 including metal vias above transistors and below top via structure) located beneath the top via structure (320, 330).
Regarding claim 14, Park as modified teaches the interconnect structure of Claim 13, and FIG. 5 of Venugopal further teaches further comprising a diffusion barrier layer (another instance of 350) separating the top via structure (320, 330) from the metal level (level of 300 including metal vias above transistors and below top via structure).
Regarding claim 15, Park as modified teaches the interconnect structure of Claim 1, and FIG. 10 of Park in view of Venugopal and Bonilla further teaches further comprising a dielectric layer (106) embedding the top via structure (104, 802) and the 2D material layer (350 of Venugopal in view of Bonilla) that is present on the top via structure (104, 802 ¶ [0022]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Venugopal and Bonilla, and further in view of Song et al. (US 10134628 B2; hereinafter Song).
Regarding claim 6, Park as modified teaches the interconnect structure of Claim 4.
Park as modified does not teach wherein the first 2D material layer is composed of a 2D material that is compositionally different than a 2D material that provides the second 2D material layer.
FIG. 20-21 of Song teaches an interconnect structure (e.g. FIG. 21 col. 14/lines 11-13) comprising: a diffusion barrier layer (B20) including a first 2D material layer (b1) and a second 2D material layer (b2), wherein the first 2D material layer (b1) is composed of a 2D material that is compositionally different than a 2D material that provides the second 2D material layer (b2 col. 13/line 57-col. 14/line 10).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the interconnect structure taught by Park with the diffusion barrier layer taught by Song for the purpose of obtaining excellent diffusion barrier effects (col. 13/line 65-col. 14/line 1).
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Venugopal, and further in view of Bonilla.
Regarding claim 16, FIGS. 8-10 of Park teach an interconnect structure (e.g. FIG. 10) comprising: a top via structure (104, 802) comprising a via (802 ¶ [0032]) located on a line (104 ¶ [0020]), wherein the via (802) and line (104) are composed of an electrically conductive material (¶ [0035],[0021]); an upper line structure (1002 ¶ [0034]) located on top of the via (802) and orientated perpendicular to the line of the top via structure (104, see FIG. 8).
Park does not teach a continuous 2D material covering an entirety of the upper line structure and the top via structure.
FIG. 12 of Bonilla teaches a conductive layer (28’) and a continuous 2D material (24’) covering an entirety of the conductive layer (28’ ¶ [0047],[0058],[0064]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the interconnect structure taught by Park with the continuous 2D material taught by Bonilla for the purpose of improving electromigration resistance (¶ [0024]) and providing a diffusion barrier/capping layer with high conductivity (¶ [0047]).
Regarding claim 17, Park as modified teaches the interconnect structure of Claim 16, and Bonilla further teaches wherein continuous 2D material is composed of graphene, TaS2, MoS2, or WSe2 (e.g. graphene ¶ [0024]-[0025]).
Allowable Subject Matter
Claims 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 9 recites the interconnect structure of Claim 1, wherein each of the top via structure and the upper line structure is composed of a non-conductive material.
Park in view of Venugopal and Bonilla teach the interconnect structure of Claim 1.
However, the prior art fails to teach or reasonably suggest “wherein each of the top via structure and the upper line structure is composed of a non-conductive material” together with all the limitations of claims 1 and 9 as claimed.
Claims 18-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 18 recites an interconnect structure comprising: a top via structure comprising a via located on a line, wherein the via and line are composed of a non-conductive material; an upper line structure located on top of the via and orientated perpendicular to the line of the top via structure; and a continuous 2D material covering an entirety of the upper line structure and the top via structure.
FIGS. 8-10 of Park teach an interconnect structure (e.g. FIG. 10) comprising: a top via structure (104, 802) comprising a via (802 ¶ [0032]) located on a line (104 ¶ [0020]), wherein the via (802) and line (104) are composed of an electrically conductive material (¶ [0035],[0021]); an upper line structure (1002 ¶ [0034]) located on top of the via (802) and orientated perpendicular to the line of the top via structure (104, see FIG. 8).
FIG. 12 of Bonilla teaches a conductive layer (28’) and a continuous 2D material (24’) covering an entirety of the conductive layer (28’ ¶ [0047],[0058],[0064]).
However, the prior art fails to teach or reasonably suggest “wherein the via and line are composed of a non-conductive material” together with all the limitations of claim 18 as claimed. Claims 19-20 are allowable insofar as they depend upon and require all the limitations of claim 18.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nora T. Nix/Assistant Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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